From: Mark Brown <broonie@kernel.org>
To: shao.mingyin@zte.com.cn
Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, pjw@kernel.org,
samuel.holland@sifive.com
Subject: Re: [PATCH v2] spi: sifive: clamp the clock divider to the register range
Date: Tue, 10 Nov 2026 16:04:06 +0000 [thread overview]
Message-ID: <b3828c22-e7ea-4858-96b3-51ecdfee3a89@sirena.org.uk> (raw)
In-Reply-To: <20261110225741763HzyrdGiR7ZOAU1NiFmCCZ@zte.com.cn>
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On Tue, Nov 10, 2026 at 10:57:41PM +0800, shao.mingyin@zte.com.cn wrote:
> From: Shao Mingyin <shao.mingyin@zte.com.cn>
>
> sifive_spi_prep_transfer() divides by t->speed_hz, which can remain
> zero when neither the device nor the controller provides a maximum
> speed. For a nonzero but very low speed, masking the divider to 12 bits
> can also wrap it to a small value and program a much faster clock.
This was previously part of a series of five patches, I see you've
resent two of them as independent patches when I was expecting the
standard workflow which would be to revise the series. This makes
things difficult to track, I'd discarded the old version waiting for the
new one.
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prev parent reply other threads:[~2026-11-10 16:04 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 14:57 shao.mingyin
2026-11-10 16:04 ` Mark Brown [this message]
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