From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD1D92DF3EA; Thu, 30 Jul 2026 06:05:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785391550; cv=none; b=nx04uWSCxXJ5Mb8G0Ym/kI3W9C+4IgyMsKDpYoi2Jle7dnHu7/gmoIIS9eDQvJMY3VjMZbMrZvuvGdCS/tPydLj5KTjGmutreNcfFP71q+/2SHedDGlR5PngXOkR0cIjSqCRImx2yjJ6g8viLhUdgx14HKuHrGrldgLWTFEeryw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785391550; c=relaxed/simple; bh=uiB0EE/8XSkvECoRR/FTm2jzKxQVCu56EfC9z+qprv8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mNT2dv0spjSZ4hsevjIpEP7SZ3WweJmW6yYaT4OZAp3XIMWbunwrBB31Tl8W6r5QECkfHEqbLspcL3Ed9RtLCobpunv7eRoVdtFGM5ZFH9fI4wKVBEKhOMjbF55nP0P9vX1Th4qtrua+q2WXH856WxKg0RsSNx24KztJJb4in/c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GtamCXF8; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GtamCXF8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 837171F000E9; Thu, 30 Jul 2026 06:05:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785391549; bh=tAOuAVsCjjlXv5KkLTD4QdgQYPCwzqX1BB1iFUTAalc=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=GtamCXF8LsNyuOtX0bFxte6e2wpAFTZv/HNUf8fbyJRtGzD2RtVKpHyfR7BTefAUc lyejbFVWXRUBerhfdz6fFxKKF/VE2YlLN0RA5dFRRyhICMdknBSxe6t8ltf2L5GWxw ty6/iuEycnSkWed9HPy7BhNdZMiJres9bW37FY2SJTW6PEoI1qDJjx8h1360uLPvsq ETUtZ4wRJLhGBqTcnNsiOB1BBdmfXlAW+F+NCQpO3uWGOny6ZtgQvvzYchJIOz7Jwj +qDSS7PlGWqES7rimkkrHG5C6nGUvgK/FK0N3LV9M08t512ZcQmOXPSted6kzAMsSb 5wAZLNDk3apMw== Message-ID: Date: Thu, 30 Jul 2026 08:05:45 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 00/14] serial: 8250: add Moxa MUEx50 PCIe board support To: Crescent Hsieh , Greg Kroah-Hartman , Andy Shevchenko Cc: FangpingFP.Cheng@moxa.com, Epson.Chiang@moxa.com, EddieSY.Lin@moxa.com, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org References: <20260729060602.492430-1-crescentcy.hsieh@moxa.com> Content-Language: en-US From: Jiri Slaby Autocrypt: addr=jirislaby@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29. 07. 26, 8:05, Crescent Hsieh wrote: > This series consolidates Moxa PCIe multiport serial board support under a > dedicated 8250_mxpcie driver and adds MUEx50 UART support needed by these > boards. > > The first part splits the existing Moxa PCIe board handling out of > 8250_pci into a separate driver while preserving the existing probe flow > and device IDs. The series then introduces the MUEx50 UART port type and > enables the board-specific UART setup, including enhanced mode and FIFO > trigger programming. > > The driver adds hardware-assisted flow control support for MUEx50 UARTs, > including automatic RTS/CTS handling and XON/XOFF offload. It also adds a > custom IRQ path and uses the MUEx50 memory-mapped FIFO windows to improve > RX and TX data movement. > > Later patches add serial interface mode switching, RS485 break handling, > and per-port private state for MUEx50-specific configuration. The driver > supports switching the serial interface mode through the RS485 > configuration path, covering RS232, RS422, and RS485 modes supported by > the boards. > > The final part extends 8250 core callbacks where needed so low-level > drivers can override break control and rx_trig_bytes handling. The > 8250_mxpcie driver uses these hooks to implement RS485 break handling via > MUEx50 features and to expose the MUEx50 programmable RX trigger level > through the generic rx_trig_bytes sysfs interface. > > --- > Changes in v4: This looks very well from my POV, except the two nits. Thanks for this. Let's see what others say ;). -- js suse labs