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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id et2-20020a056214176200b0067f02d13157sm804679qvb.15.2023.12.14.02.13.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Dec 2023 02:13:42 -0800 (PST) Message-ID: Date: Thu, 14 Dec 2023 11:13:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] KVM: selftests: aarch64: Fix the buggy [enable|disable]_counter Content-Language: en-US To: Shaoqin Huang , Marc Zyngier , Oliver Upton , kvmarm@lists.linux.dev Cc: James Morse , Suzuki K Poulose , Zenghui Yu , Paolo Bonzini , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org References: <20231129072712.2667337-1-shahuang@redhat.com> <20231129072712.2667337-4-shahuang@redhat.com> From: Eric Auger In-Reply-To: <20231129072712.2667337-4-shahuang@redhat.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Shaoqin, On 11/29/23 08:27, Shaoqin Huang wrote: > In general, the set/clr registers should always be used in their > write form, never in a RMW form (imagine an interrupt disabling > a counter between the read and the write...). > > The current implementation of [enable|disable]_counter both use the RMW > form, fix them by directly write to the set/clr registers. > > At the same time, it also fix the buggy disable_counter() which would > end up disabling all the counters. > > Signed-off-by: Shaoqin Huang Reviewed-by: Eric Auger Eric > --- > tools/testing/selftests/kvm/include/aarch64/vpmu.h | 8 ++------ > 1 file changed, 2 insertions(+), 6 deletions(-) > > diff --git a/tools/testing/selftests/kvm/include/aarch64/vpmu.h b/tools/testing/selftests/kvm/include/aarch64/vpmu.h > index e0cc1ca1c4b7..644dae3814b5 100644 > --- a/tools/testing/selftests/kvm/include/aarch64/vpmu.h > +++ b/tools/testing/selftests/kvm/include/aarch64/vpmu.h > @@ -78,17 +78,13 @@ static inline void write_sel_evtyper(int sel, unsigned long val) > > static inline void enable_counter(int idx) > { > - uint64_t v = read_sysreg(pmcntenset_el0); > - > - write_sysreg(BIT(idx) | v, pmcntenset_el0); > + write_sysreg(BIT(idx), pmcntenset_el0); > isb(); > } > > static inline void disable_counter(int idx) > { > - uint64_t v = read_sysreg(pmcntenset_el0); > - > - write_sysreg(BIT(idx) | v, pmcntenclr_el0); > + write_sysreg(BIT(idx), pmcntenclr_el0); > isb(); > } >