From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 606581C84D5; Wed, 30 Apr 2025 04:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745987456; cv=none; b=BPytZOiSEm6Hl4Ge2PhsqsJVPV0i0pwl28ZeLiYIOsSFjlAPS9UZbzI0yMPnLVIBmraEzVvWUpJPtw3jgfaAbGbtuXaPcbnQQAI8naHXX6I9WvQWVuePpEgSR04WmMGUjPYFsn7vYqGvZoc7ER1DxxUv1egY2k2Z2nsOiA7BL5g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745987456; c=relaxed/simple; bh=Pit2CgoCB0xiMreoMAw4nX84ze5/3nKJOIzfhujSJ5g=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=UrJKZ9zPOZIRJhTorME6AARXSzQhVV+2whRCdvXqfeJGOUrKClNOVFokNGQvLJ0M9LGg7H/5joT4F0MfchVNOVLVnk+RE2HC8bNsS7L5oksA3rA9lW3FjDmxt7QWQE9omwcIOsTtPt/4ktc2J1991BDNLUOUKYops76lakx4gU4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MB4UNh+O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MB4UNh+O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7ED90C4CEE9; Wed, 30 Apr 2025 04:30:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745987455; bh=Pit2CgoCB0xiMreoMAw4nX84ze5/3nKJOIzfhujSJ5g=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=MB4UNh+OqYAjIaIqEP1X731zD1floqa80U7If1kq1hNkMNeAOHfHcyZzY9bouzHjs pahraQp/lHQI17uG06fZ9JiJS4FU6ZredOu9jc0DdcJPLzdLML7AbJspvtmsBqLjyK bCc26bCzexTFnfi8KKaZqzws4ttIT18luTIqjWmXybWLq7LmlJpNyomYtOkvaMqQjB CUK3y8Dhttk4LIyts3E8cuR0gopxHyKIxqMEB3hY3JoYCkhx9vi2xTaMwOixi4BU5c X4NjeaCxdzSxTxf4h2TZmMa1f9llJqPahN/LdZlpJsj7t0B2+fzGn4QZLhYlN8StON rlF4Id+XCX+sQ== Message-ID: Date: Wed, 30 Apr 2025 06:30:51 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] serial: qcom-geni: Enable support for half-duplex mode To: Anup Kulkarni , gregkh@linuxfoundation.org, johan+linaro@kernel.org, dianders@chromium.org, konradybcio@kernel.org, u.kleine-koenig@baylibre.com, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: andersson@kernel.org, quic_msavaliy@quicinc.com, quic_vdadhani@quicinc.com References: <20250429104339.321962-1-quic_anupkulk@quicinc.com> Content-Language: en-US From: Jiri Slaby Autocrypt: addr=jirislaby@kernel.org; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 29. 04. 25, 12:43, Anup Kulkarni wrote: > Currently the RTS pin is used as flow control in the UART controller by > default.For half-duplex modes, use the RTS pin for direction control to > prevent data collisions by allowing only one direction at a time. Utilize > the rs485 structure and callbacks in the serial core framework to support > half-duplex modes. Use the IOCTL value, 'TIOCSRS485', and the 'struct > serial_rs485' supported by the serial framework to implement support for > related callbacks. Enable RS485 mode with these callbacks. > > Signed-off-by: Anup Kulkarni > --- > drivers/tty/serial/qcom_geni_serial.c | 61 ++++++++++++++++++++++++++- > 1 file changed, 60 insertions(+), 1 deletion(-) > > diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c > index a80ce7aaf309..ad3c63cecda0 100644 > --- a/drivers/tty/serial/qcom_geni_serial.c > +++ b/drivers/tty/serial/qcom_geni_serial.c ... > @@ -637,6 +650,7 @@ static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) > struct tty_port *tport = &uport->state->port; > unsigned int xmit_size; > u8 *tail; > + bool pin_state; > int ret; > > if (port->tx_dma_addr) > @@ -648,6 +662,12 @@ static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) > xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail, > UART_XMIT_SIZE); > > + if (uport->rs485.flags & SER_RS485_ENABLED) { > + /* For RS485 mode, the RTS can be set/cleared before transmission */ > + pin_state = !!(uport->rs485.flags & SER_RS485_RTS_ON_SEND); That !! is unnecessary. > + qcom_geni_set_rts_pin(uport, pin_state); > + } > + > qcom_geni_serial_setup_tx(uport, xmit_size); > > ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size, ... > @@ -1055,8 +1076,17 @@ static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) > } > > if (dma) { > - if (dma_tx_status & TX_DMA_DONE) > + if (dma_tx_status & TX_DMA_DONE) { > qcom_geni_serial_handle_tx_dma(uport); > + // Check if RS485 mode is enabled > + if (uport->rs485.flags & SER_RS485_ENABLED) { > + // Determine the RTS pin state based on the > + // RS485 RTS_AFTER_SEND flag. > + pin_state = !!(uport->rs485.flags & SER_RS485_RTS_AFTER_SEND); The same here. > + // Set or clear the RTS pin according to the determined state > + qcom_geni_set_rts_pin(uport, pin_state); > + } > + } > > if (dma_rx_status) { > if (dma_rx_status & RX_RESET_DONE) > @@ -1594,6 +1624,29 @@ static void qcom_geni_serial_pm(struct uart_port *uport, > } > } > > +/** > + * qcom_geni_rs485_config - Configure RS485 settings for the UART port > + * @uport: Pointer to the UART port structure > + * @termios: Pointer to the termios structure > + * @rs485: Pointer to the RS485 configuration structure > + * > + * This function configures the RTS (Request to Send) pin behavior for RS485 mode. > + * When RS485 mode is enabled, the RTS pin is kept in the ACTIVE state. > + * When RS485 mode is disabled, the RTS pin is controlled by the QUP hardware for auto flow control. > + * > + * Return: Always returns 0. > + */ > + This \n is superfluous. IIRC it is even problematic for kernel-doc. > +static int qcom_geni_rs485_config(struct uart_port *uport, > + struct ktermios *termios, struct serial_rs485 *rs485) > +{ > + if (rs485->flags & SER_RS485_ENABLED) > + qcom_geni_set_rts_pin(uport, true); // Set RTS pin to ACTIVE state C style comments ^^ and vv. > + else > + writel(0, uport->membase + SE_UART_MANUAL_RFR); // Revert to auto flow control > + return 0; > +} > + > static const struct uart_ops qcom_geni_console_pops = { > .tx_empty = qcom_geni_serial_tx_empty, > .stop_tx = qcom_geni_serial_stop_tx_fifo, thanks, -- js suse labs