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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-3a18aadb151sm4149081fa.20.2026.08.19.04.26.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 Aug 2026 04:26:13 -0700 (PDT) Message-ID: Date: Wed, 19 Aug 2026 14:26:12 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/5] i2c: qcom-cci: Add 19.2 MHz timings for the v2 CCI To: Loic Poulain , Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konradybcio@kernel.org, stephan.gerhold@linaro.org References: <20260801-cci-clk-fix-v4-0-e1d80da54e01@oss.qualcomm.com> <20260801-cci-clk-fix-v4-3-e1d80da54e01@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20260801-cci-clk-fix-v4-3-e1d80da54e01@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 8/1/26 23:10, Loic Poulain wrote: > The v2 CCI (msm8996/sdm630/msm8953/...) is normally clocked at 37.5 MHz, > but its CCI clock can also be configured and run at 19.2 MHz. Add the > Standard and Fast timing sets calibrated for 19.2 MHz so that a v2 > controller left at that rate still has valid timings for those modes > (Fast+ requires 37.5 MHz). > > The values mirror the v1/v1.5 19.2 MHz Standard/Fast timings, which > share the same CCI clock rate. > > Signed-off-by: Loic Poulain > --- > drivers/i2c/busses/i2c-qcom-cci.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > index 1092ce0371429ef64c7cc44cc23a42ba4c135af5..b6fa37a306758ec33ede6fcc39ce4412b86d9a84 100644 > --- a/drivers/i2c/busses/i2c-qcom-cci.c > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -762,6 +762,30 @@ static const struct cci_data cci_v2_data = { > .max_write_len = 11, > .max_read_len = 12, > }, > + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] = { > + .thigh = 78, > + .tlow = 114, > + .tsu_sto = 28, > + .tsu_sta = 28, > + .thd_dat = 10, > + .thd_sta = 77, > + .tbuf = 118, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 1 > + }, > + .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] = { > + .thigh = 20, > + .tlow = 28, > + .tsu_sto = 21, > + .tsu_sta = 21, > + .thd_dat = 13, > + .thd_sta = 18, > + .tbuf = 32, > + .scl_stretch_en = 0, > + .trdhld = 6, > + .tsp = 3 > + }, > .params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] = { > .thigh = 201, > .tlow = 174, > Reviewed-by: Vladimir Zapolskiy -- Best wishes, Vladimir