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[83.9.1.63]) by smtp.gmail.com with ESMTPSA id v18-20020a2e7a12000000b002ad8174d025sm1674711ljc.122.2023.06.23.03.22.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Jun 2023 03:22:44 -0700 (PDT) Message-ID: Date: Fri, 23 Jun 2023 12:22:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 1/4] pcie: qcom: Fix the macro PARF_SLV_ADDR_SPACE_SIZE_2_3_3 Content-Language: en-US To: Sricharan Ramabadhran , agross@kernel.org, andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com, mani@kernel.org, lpieralisi@kernel.org, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org References: <20230623094403.3978838-1-quic_srichara@quicinc.com> <20230623094403.3978838-2-quic_srichara@quicinc.com> From: Konrad Dybcio In-Reply-To: <20230623094403.3978838-2-quic_srichara@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23.06.2023 11:44, Sricharan Ramabadhran wrote: > PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro used for IPQ8074 > pcie slave addr size was initially set to 0x358, but > was wrongly changed to 0x168 as a part of > 'PCI: qcom: Sort and group registers and bitfield definitions' Surely not, this commit only moved the definition containing 0x358 up. Konrad > Fixing it back to right value here. > > Without this pcie bring up on IPQ8074 is broken now. > > Fixes: 769e49d87b15 ("PCI: qcom: Sort and group registers and bitfield definitions") > Signed-off-by: Sricharan Ramabadhran > --- > drivers/pci/controller/dwc/pcie-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 4ab30892f6ef..59823beed13f 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -43,7 +43,7 @@ > #define PARF_PHY_REFCLK 0x4c > #define PARF_CONFIG_BITS 0x50 > #define PARF_DBI_BASE_ADDR 0x168 > -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ > +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x358 /* Register offset specific to IP ver 2.3.3 */ > #define PARF_MHI_CLOCK_RESET_CTRL 0x174 > #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8