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Thu, 16 Apr 2026 16:29:33 -0700 From: Nicolin Chen To: Will Deacon , Robin Murphy , "Joerg Roedel" , Bjorn Helgaas , "Jason Gunthorpe" CC: "Rafael J . Wysocki" , Len Brown , Pranjal Shrivastava , Mostafa Saleh , Lu Baolu , Kevin Tian , , , , , , , Shuai Xue Subject: [PATCH v3 10/11] iommu/arm-smmu-v3: Introduce master->ats_broken flag Date: Thu, 16 Apr 2026 16:28:39 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E80:EE_|BL1PR12MB5996:EE_ X-MS-Office365-Filtering-Correlation-Id: 7f18b5f4-6b3c-493e-4433-08de9c10198a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|7416014|36860700016|376014|18002099003|22082099003|56012099003|11006099003; X-Microsoft-Antispam-Message-Info: h8/wZ0WnMrzk7tyGjFrjO44ziq1JtowcO8qrJvr2liKfeFIl114o/vSEYvKHvOH7CMxYCs3j9x6GzC+IJG5CV/Z3lBQ5ZaHmb4j6tSup1fB+3pB/E2QPQFAe2H640lq24QpuMwGy195eyM832Qm6yWCo1RnK0FmswVCoccDeZ275ilG+NPK3eYxAm1ha3M3mM/o+6jr3cBzICfEQSAdkOod1p3jX3Wl4ISlBYhz70R7lCQmFbqaXYBCXn1Y6yW3Xs8qrmfeLn8oxcxGYWdO8/qby0D7mhQ2fshAHClRL25tUkIlgCPqz7Wc0Y5jluRzGUHhMeHr7eWNc/E4BPLs+hdYx1xymFOiRQ0hANannaJ4DveoFZ4ZfBPUhg+kpzJHM9VBj8WEytHAUlMeGsbuYU+C6fy7bNv+tthojQGsgg7k18qIl0UrJkgy/JQYEgdG3NJiw7POr8cc+naxG+Avi/dJSoOu60mqS0dcXfhcPGMPiCFmc5peDHse9TXp0olDkkhOqyWMqe0dHIQj+8twBfj5UT6iH0KeGze0/3rIQCAj5cCcj6kOipDUTEyMfOIhqXsYXoye8emBl3VngcEGUek/tWZEIK57LSlg+EJ6W35Q2A6T4O/8JpskHtyDAKQfCDQeQh8WXDt22A1IKfPm1t9ZdmEI5vjtlhVS3xZ8zikvPr0lZ4yuVrntOsXHw6bGrpXVNBpG+2rbjqQGajB0hdcdR+JFutXzvqVKp+FDjnwEpHgS6lCP2xTjDMBOtoyYg/4PA6nZvL6oxRSpuIegoHg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(36860700016)(376014)(18002099003)(22082099003)(56012099003)(11006099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vpJJ+3c+4nJnCG81mwHINtEH/cDkt0E6RbB7H1qynykpKINfr6xv4FLGLIHDrzAT409uUku3PxyMRGfjU8RF/Te6PQp7oybIEfpdq0enGJB0GLBlmqd/FGIKUkxmCB1/3glLuOpJA/vtM1sSAtLT+2U3a/C+nIwLEmLCw8mmuFWL+RrIeh13bBP0tKmdewNZagMCMU7KCl3Eq1AVjuIbdCK5twKsDy0WHt4BgozUu/X9dfmfexkhYCO1AuYFd5mOjQCIs2qpppNKN1JWgEeFdUOdDAvPncI+NNP4JvPz3Y/AKcz/H/SiZ2ROHhNgzoI/9lHnENLz1nsgB8SDJgBDXbaiLOmoo6KkBx4WzHwxB2gDJntvElE8ErfzqQpmMFkE66xlOO+822xUEhVQMFni9M5AzYQaPSwGMEHQPzdkR8vUtChmqg5CEXTYn+4tezkT X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2026 23:30:09.4579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f18b5f4-6b3c-493e-4433-08de9c10198a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E80.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5996 The flag will be set when IOMMU cannot trust device's ATS function. E.g., when ATC invalidation request to the device times out. Once it is set, unsupport the ATS feature to prevent data corruption, and skip further ATC invalidation commands to avoid new timeouts. Unset the flag when the device finishes a reset for recovery. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 26e0ee0bb5b45..95bce9966374a 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -941,6 +941,7 @@ struct arm_smmu_master { /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; + bool ats_broken; bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 13f225f704e73..5dead82cf1186 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2523,6 +2523,10 @@ static int arm_smmu_atc_inv_master(struct arm_smmu_master *master, struct arm_smmu_cmdq_ent cmd; struct arm_smmu_cmdq_batch cmds; + /* Do not issue ATC_INV that will definitely time out */ + if (READ_ONCE(master->ats_broken)) + return 0; + arm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd); arm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd); @@ -2729,11 +2733,17 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs, arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); break; case INV_TYPE_ATS: + /* Do not issue ATC_INV that will definitely time out */ + if (READ_ONCE(cur->master->ats_broken)) + break; arm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd); cmd.atc.sid = cur->id; arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); break; case INV_TYPE_ATS_FULL: + /* Do not issue ATC_INV that will definitely time out */ + if (READ_ONCE(cur->master->ats_broken)) + break; arm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd); cmd.atc.sid = cur->id; arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); @@ -3069,6 +3079,15 @@ void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, } } +static void arm_smmu_reset_device_done(struct device *dev) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + + if (WARN_ON(!master)) + return; + WRITE_ONCE(master->ats_broken, false); +} + static bool arm_smmu_ats_supported(struct arm_smmu_master *master) { struct device *dev = master->dev; @@ -3081,6 +3100,14 @@ static bool arm_smmu_ats_supported(struct arm_smmu_master *master) if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) return false; + /* + * Do not enable ATS if master->ats_broken is set. The PCI device should + * go through a recovery (reset) that shall notify the SMMUv3 driver via + * a reset_device_done callback. + */ + if (READ_ONCE(master->ats_broken)) + return false; + return dev_is_pci(dev) && pci_ats_supported(to_pci_dev(dev)); } @@ -4412,6 +4439,7 @@ static const struct iommu_ops arm_smmu_ops = { .domain_alloc_paging_flags = arm_smmu_domain_alloc_paging_flags, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, + .reset_device_done = arm_smmu_reset_device_done, .device_group = arm_smmu_device_group, .of_xlate = arm_smmu_of_xlate, .get_resv_regions = arm_smmu_get_resv_regions, -- 2.43.0