From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from codeconstruct.com.au (pi.codeconstruct.com.au [203.29.241.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1B0C1FDE31 for ; Thu, 4 Jun 2026 00:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.29.241.158 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780533850; cv=none; b=UrqiPsNOiAraIsCqj4MHFVXeLyevhQrnLjiWdsq4bSCIdljLLm6/Xvv7N/2TN1uiWkZpRpvDn6Pcpml5itTY4M4hcKqX4Ve9UdbfqJXiuOFexfsBNnIiwjsB650HSwWD7sPcH3BO0V+Tm+3vJoc0uu/euSZaENskU2Bq8ahRC/Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780533850; c=relaxed/simple; bh=YdWND3qRTxK7EV4rgG+5r+IKFe6OcNY8oDGcjYYbHTg=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=EVGkM2fEwh98AwYI5D+MHo6iXflfKJiNFDlaQbiegHVyGCS0D8Al0SmXeaGmNbeRNodV6LszY8DGy84AFCV854JiVunxFbIygEiGvyYaQiPDLU0xoLAG4fPbZqFg13VNu4YdzOGWcfhLctlhSn2TdqB0tBy7+6PK80MPKtwr+pY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=codeconstruct.com.au; spf=pass smtp.mailfrom=codeconstruct.com.au; dkim=pass (2048-bit key) header.d=codeconstruct.com.au header.i=@codeconstruct.com.au header.b=OQHG4L6g; arc=none smtp.client-ip=203.29.241.158 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=codeconstruct.com.au Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=codeconstruct.com.au Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=codeconstruct.com.au header.i=@codeconstruct.com.au header.b="OQHG4L6g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1780533846; bh=WViDnFCt/53zZbNSkHdGljjmM4CdgEj/SmGmLtUaRpM=; h=Subject:From:To:Cc:Date:In-Reply-To:References; b=OQHG4L6gZtKNWzS2bY6TgmSx46oPhsaeYK1rEiwiJoFnlr0JzVgO3rXzJm73ycREJ fyya/WEj9/15BXXvVYonPRSaUitrXxDZRLQ0cteWDOg1Id/1lD81xoRdOdkr16eCHB 8fI7Kn+KJHFW8NgYmWV2gPmx1N+WdURW+kKsr4eiLTYPzPuIbk2kg1pQad2A1jwMAL K+KbM40QCAcHGV6hexj5GhhGuLNP6QlomKiBAOSgj8m6jKUhUjIkFQHAwEBqe/6CQh exNwKi3TLCn9rypG1b0WF5tJ1hW8l7rNcckmSjMd94XbQadU3SwR4GFlknkIapUEl6 X28Nj0tPFbNMA== Received: from [192.168.68.117] (unknown [180.150.112.11]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id C556B60288; Thu, 4 Jun 2026 08:44:04 +0800 (AWST) Message-ID: Subject: Re: [PATCH v1 2/2] soc: aspeed: add host-side PCIe BMC device driver From: Andrew Jeffery To: Andrew Lunn , =?ISO-8859-1?Q?Gr=E9goire?= Layet Cc: joel@jms.id.au, jacky_chou@aspeedtech.com, yh_chung@aspeedtech.com, ninad@linux.ibm.com, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Thu, 04 Jun 2026 10:14:03 +0930 In-Reply-To: <77464543-f793-4441-9fce-8666ba1c3d66@lunn.ch> References: <77464543-f793-4441-9fce-8666ba1c3d66@lunn.ch> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-0+deb13u1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-06-03 at 16:30 +0200, Andrew Lunn wrote: > On Wed, Jun 03, 2026 at 03:43:36PM +0200, Gr=C3=A9goire Layet wrote: > > > How virtual is this? Is this directly accessing the hardware via > > > shared memory? Or is there software on the BMC which traps these > > > reads/writes and responds? > >=20 > > The VUART is virtual because there is no physical UART link between > > the host and the BMC. > > Instead, the AST2600 exposes a 16550-compatible register set on both > > sides (BMC APB and PCIe host MMIO). > > The data flows using an internal 16 byte FIFO shared between the two > > register views. > > So it's hardware emulated and there is no software in the data path. > >=20 > > The AST2600 has four VUARTs, two of which are accessible via PCIe MMIO. > > This is based on the following section of the AST2600 datasheet: > > III.48 VUART and III.64 PCI2VUART. > >=20 > > Because the silicon presents a standard 16550A interface in hardware, > > the existing 8250 driver works without modification. >=20 > So tell us about security. >=20 > Is only this UART exposed in the shared memory? >=20 No, however the BMC PCI interface provides a PCI-to-LPC bridge, so PCI accesses can drive cycles in to e.g LPC IO devices exposed by the BMC. > So the memory window > is 8 bytes wide? Or are there other peripherals also exposed? How do > we know the aspeed is not using the UART itself? >=20 For the "regular" SuperIO-controlled UARTs this is a concern, but it's not a concern for the VUARTs. Each VUART has a pair of 8250 register sets, one accessible from the BMC, the other accessible to the host, where both interfaces share the FIFOs to propagate data. > If two drivers are > using it, are we going to crash one or the other system? By the above, not for the VUARTs. >=20 > https://en.wikipedia.org/wiki/Core_War >=20 > The advantage of rpmsg is that the aspeed would advertise what > services it is willing to expose. The security issues are different, > implementation bugs vs exposing bits of hardware to an attacker. >From my understanding rpmsg seems like a reasonable fit for the mailbox functionality. Andrew