From: "Arnd Bergmann" <arnd@arndb.de>
To: "Herve Codina" <herve.codina@bootlin.com>,
"Geert Uytterhoeven" <geert@linux-m68k.org>,
"Andy Shevchenko" <andy.shevchenko@gmail.com>,
"Simon Horman" <horms@kernel.org>, "Lee Jones" <lee@kernel.org>,
"derek.kiernan@amd.com" <derek.kiernan@amd.com>,
"dragan.cvetic@amd.com" <dragan.cvetic@amd.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Lars Povlsen" <lars.povlsen@microchip.com>,
"Steen Hegelund" <Steen.Hegelund@microchip.com>,
"Daniel Machon" <daniel.machon@microchip.com>,
UNGLinuxDriver@microchip.com, "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Saravana Kannan" <saravanak@google.com>
Cc: "David S . Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Jakub Kicinski" <kuba@kernel.org>,
"Paolo Abeni" <pabeni@redhat.com>,
"Horatiu Vultur" <horatiu.vultur@microchip.com>,
"Andrew Lunn" <andrew@lunn.ch>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Netdev <netdev@vger.kernel.org>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
"Allan Nielsen" <allan.nielsen@microchip.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH v6 3/7] misc: Add support for LAN966x PCI device
Date: Wed, 02 Oct 2024 11:08:15 +0000 [thread overview]
Message-ID: <b4602de6-bf45-4daf-8b52-f06cc6ff67ef@app.fastmail.com> (raw)
In-Reply-To: <20240930121601.172216-4-herve.codina@bootlin.com>
On Mon, Sep 30, 2024, at 12:15, Herve Codina wrote:
> + pci-ep-bus@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + /*
> + * map @0xe2000000 (32MB) to BAR0 (CPU)
> + * map @0xe0000000 (16MB) to BAR1 (AMBA)
> + */
> + ranges = <0xe2000000 0x00 0x00 0x00 0x2000000
> + 0xe0000000 0x01 0x00 0x00 0x1000000>;
I was wondering about how this fits into the PCI DT
binding, is this a child of the PCI device, or does the
"pci-ep-bus" refer to the PCI device itself?
Where do the "0x01 0x00 0x00" and "0x00 0x00 0x00" addresses
come from? Shouldn't those be "02000010 0x00 0x00" and
"02000014 0x00 0x00" to refer to the first and second
relocatable 32-bit memory BAR?
Arnd
next prev parent reply other threads:[~2024-10-02 11:10 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-30 12:15 [PATCH v6 0/7] Add support for the LAN966x PCI device using a DT overlay Herve Codina
2024-09-30 12:15 ` [PATCH v6 1/7] dt-bindings: reset: microchip,rst: Allow to replace cpu-syscon by an additional reg item Herve Codina
2024-10-01 6:43 ` Krzysztof Kozlowski
2024-10-01 16:06 ` Herve Codina
2024-09-30 12:15 ` [PATCH v6 2/7] reset: mchp: sparx5: Use the second reg item when cpu-syscon is not present Herve Codina
2024-09-30 13:03 ` Steen Hegelund
2024-09-30 13:23 ` Geert Uytterhoeven
2024-09-30 13:57 ` Arnd Bergmann
2024-09-30 14:26 ` Herve Codina
2024-10-01 16:30 ` Herve Codina
2024-10-02 9:29 ` Arnd Bergmann
2024-10-02 10:19 ` Herve Codina
2024-10-02 10:58 ` Arnd Bergmann
2024-09-30 12:15 ` [PATCH v6 3/7] misc: Add support for LAN966x PCI device Herve Codina
2024-10-02 11:08 ` Arnd Bergmann [this message]
2024-10-02 12:41 ` Herve Codina
2024-10-02 14:31 ` Arnd Bergmann
2024-10-02 16:02 ` Herve Codina
2024-09-30 12:15 ` [PATCH v6 4/7] MAINTAINERS: Add the Microchip LAN966x PCI driver entry Herve Codina
2024-09-30 12:15 ` [PATCH v6 5/7] reset: mchp: sparx5: Add MCHP_LAN966X_PCI dependency Herve Codina
2024-09-30 12:15 ` [PATCH v6 6/7] reset: mchp: sparx5: Allow building as a module Herve Codina
2024-09-30 12:15 ` [PATCH v6 7/7] reset: mchp: sparx5: set the dev member of the reset controller Herve Codina
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