From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BBA439902C for ; Mon, 20 Apr 2026 11:43:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.222 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776685418; cv=none; b=lRxsH0u549zTmMqhXf2saU16eHHFvmRkqZsnlXzTLTPMovtRBipNpXcYhKo8X4tqqoNQxi2XS711gaTqYW/qu+Wy2A+rNnmFhimK5ks9VRmMZPzWns2FrMcAnD5/7RcVd5tZZhckNeV2BokPOqGgTsqyETYUdsXFOT2u5SgsvEg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776685418; c=relaxed/simple; bh=ehdFz075FwbMd3XnyA9/AECkp4+63TrtvVEgDub8cs0=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=R4ZTj8ccG4CUWZb0oPBX/nS7hLkeIBo6prqFlq8GrMgqlCXscEmVJcupDvQD8Y8Jp6YgGN9sPGJKI7kWES+VUvQAQzCcpC5Z4FguSFzw2K68ENbRGr+Q7aF+Ie64gMg3BMpD+EoYFFeuan2bAt1WlYBie+t1WKeQ+jiMQS673U4= ARC-Authentication-Results:i=1; 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Mon, 20 Apr 2026 19:37:10 +0800 (CST) Received: from kwepemr500001.china.huawei.com (unknown [7.202.194.229]) by mail.maildlp.com (Postfix) with ESMTPS id A1F0D40573; Mon, 20 Apr 2026 19:43:31 +0800 (CST) Received: from [10.174.179.248] (10.174.179.248) by kwepemr500001.china.huawei.com (7.202.194.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 20 Apr 2026 19:43:29 +0800 Message-ID: Date: Mon, 20 Apr 2026 19:43:20 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC v3 2/4] mm/pgtable: Make pfn_pte() filter out huge page attributes To: Will Deacon CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , References: <20260228070906.1418911-1-yintirui@huawei.com> <20260228070906.1418911-3-yintirui@huawei.com> From: Yin Tirui In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemr500001.china.huawei.com (7.202.194.229) Hi Will, On 4/20/2026 4:48 PM, Will Deacon wrote: > On Sat, Feb 28, 2026 at 03:09:04PM +0800, Yin Tirui wrote: >> A fundamental principle of page table type safety is that `pte_t` represents >> the lowest level page table entry and should never carry huge page attributes. >> >> Currently, passing a pgprot with huge page bits (e.g., extracted via >> pmd_pgprot()) into pfn_pte() creates a malformed PTE that retains the huge >> attribute, leading to the necessity of the ugly `pte_clrhuge()` anti-pattern. >> >> Enforce type safety by making `pfn_pte()` inherently filter out huge page >> attributes: >> - On x86: Strip the `_PAGE_PSE` bit. >> - On ARM64: Mask out the block descriptor bits in `PTE_TYPE_MASK` and >> enforce the `PTE_TYPE_PAGE` format. >> - On RISC-V: No changes required, as RISC-V leaf PMDs and PTEs share the >> exact same hardware format and do not use a distinct huge bit. >> >> Signed-off-by: Yin Tirui >> --- >> arch/arm64/include/asm/pgtable.h | 4 +++- >> arch/x86/include/asm/pgtable.h | 4 ++++ >> 2 files changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h >> index b3e58735c49b..f2a7a40106d2 100644 >> --- a/arch/arm64/include/asm/pgtable.h >> +++ b/arch/arm64/include/asm/pgtable.h >> @@ -141,7 +141,9 @@ static inline pteval_t __phys_to_pte_val(phys_addr_t phys) >> >> #define pte_pfn(pte) (__pte_to_phys(pte) >> PAGE_SHIFT) >> #define pfn_pte(pfn,prot) \ >> - __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) >> + __pte(__phys_to_pte_val((phys_addr_t)(pfn) << PAGE_SHIFT) | \ >> + ((pgprot_val(prot) & ~(PTE_TYPE_MASK & ~PTE_VALID)) | \ >> + (PTE_TYPE_PAGE & ~PTE_VALID))) > Why are you touching arch/arm64? We don't implement pte_clrhuge() afaict. > What does this actually fix? Originally, this patch aimed to ensure that pfn_pte() always returns a PTE without any huge page attributes by embedding the logic of pte_clrhuge() directly into pfn_pte(). However, we found this approach doesn't work well on x86, so we've abandoned this design. Following Matthew Wilcox's suggestion, the current approach is instead to have pmd_pgprot() return a 4K–formatted pgprot_t (i.e., without huge page attributes), and then explicitly add the huge page attributes when constructing a PMD via pfn_pmd(). I've already implemented this in my recent commit: https://github.com/torvalds/linux/commit/5b8ce6d33822dd7776432e03a08fe6d2dedac079 > > Will -- Yin Tirui