From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Anna Maniscalco <anna.maniscalco2000@gmail.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Konrad Dybcio <konradybcio@kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v7 05/16] drm/msm/registers: Add perfcntr json
Date: Wed, 20 May 2026 14:06:40 +0530 [thread overview]
Message-ID: <b4787a2b-c1db-4c0c-8c58-fe60fed83cfb@oss.qualcomm.com> (raw)
In-Reply-To: <20260518190735.16236-6-robin.clark@oss.qualcomm.com>
On 5/19/2026 12:36 AM, Rob Clark wrote:
> Pull in perfcntr json and wire up generation of perfcntr tables.
>
> Sync from mesa commit d2c4653ee953 ("freedreno/registers: Add gen8 perfcntrs")
>
> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
> ---
> drivers/gpu/drm/msm/Makefile | 25 +-
> drivers/gpu/drm/msm/msm_perfcntr.h | 48 ++++
> .../msm/registers/adreno/a2xx_perfcntrs.json | 109 ++++++++
> .../msm/registers/adreno/a5xx_perfcntrs.json | 128 ++++++++++
> .../msm/registers/adreno/a6xx_perfcntrs.json | 105 ++++++++
> .../msm/registers/adreno/a7xx_perfcntrs.json | 228 +++++++++++++++++
> .../msm/registers/adreno/a8xx_perfcntrs.json | 240 ++++++++++++++++++
> 7 files changed, 882 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/msm/msm_perfcntr.h
> create mode 100644 drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json
> create mode 100644 drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json
> create mode 100644 drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> create mode 100644 drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> create mode 100644 drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
>
<< snip >>
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> new file mode 100644
> index 000000000000..8bb31820479e
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_perfcntrs.json
> @@ -0,0 +1,105 @@
> +{
RBBM and CMP groups are missing here.
> + "chip": "A6XX",
> + "groups": [
> + {
> + "name": "CP",
> + "num": 14,
> + "reserved": [ 0 ],
> + "select": "CP_PERFCTR_CP_SEL",
> + "counter": "RBBM_PERFCTR_CP",
> + "countable_type": "a6xx_cp_perfcounter_select"
<< snip >>
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> new file mode 100644
> index 000000000000..e60aab1862ec
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json
> @@ -0,0 +1,228 @@
> +{
> + "chip": "A7XX",
> + "groups": [
> + {
> + "name": "CP",
> + "num": 14,
> + "reserved": [ 0 ],
> + "select": "CP_PERFCTR_CP_SEL",
> + "counter": "RBBM_PERFCTR_CP",
> + "countable_type": "a7xx_cp_perfcounter_select"
> + },
> + {
> + "name": "RBBM",
> + "num": 4,
> + "select": "RBBM_PERFCTR_RBBM_SEL",
> + "counter": "RBBM_PERFCTR_RBBM",
> + "countable_type": "a7xx_rbbm_perfcounter_select"
> + },
> + {
> + "name": "PC",
> + "pipe": "BR",
> + "num": 8,
> + "select": "PC_PERFCTR_PC_SEL",
> + "counter": "RBBM_PERFCTR_PC",
> + "countable_type": "a7xx_pc_perfcounter_select"
> + },
> + {
> + "name": "VFD",
> + "pipe": "BR",
> + "num": 8,
> + "select": "VFD_PERFCTR_VFD_SEL",
> + "counter": "RBBM_PERFCTR_VFD",
> + "countable_type": "a7xx_vfd_perfcounter_select"
> + },
> + {
> + "name": "HLSQ",
> + "pipe": "BR",
> + "num": 6,
> + "select": "SP_PERFCTR_HLSQ_SEL",
> + "counter": "RBBM_PERFCTR_HLSQ",
> + "countable_type": "a7xx_hlsq_perfcounter_select"
> + },
> + {
> + "name": "VPC",
> + "pipe": "BR",
> + "num": 6,
> + "select": "VPC_PERFCTR_VPC_SEL",
> + "counter": "RBBM_PERFCTR_VPC",
> + "countable_type": "a7xx_vpc_perfcounter_select"
> + },
> + {
> + "name": "TSE",
> + "pipe": "BR",
> + "num": 4,
> + "select": "GRAS_PERFCTR_TSE_SEL",
> + "counter": "RBBM_PERFCTR_TSE",
> + "countable_type": "a7xx_tse_perfcounter_select"
> + },
> + {
> + "name": "RAS",
> + "pipe": "BR",
> + "num": 4,
> + "select": "GRAS_PERFCTR_RAS_SEL",
> + "counter": "RBBM_PERFCTR_RAS",
> + "countable_type": "a7xx_ras_perfcounter_select"
> + },
> + {
> + "name": "UCHE",
> + "num": 12,
A740 and newer has 24 counters
> + "select": "UCHE_PERFCTR_UCHE_SEL",
> + "counter": "RBBM_PERFCTR_UCHE",
> + "countable_type": "a7xx_uche_perfcounter_select"
> + },
<< snip >>
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> new file mode 100644
> index 000000000000..503b113df397
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json
> @@ -0,0 +1,240 @@
> +{
> + "chip": "A8XX",
> + "groups": [
> + {
> + "name": "CP",
> + "num": 14,
> + "reserved": [ 0 ],
> + "select": "CP_PERFCTR_CP_SEL",
> + "counter": "RBBM_PERFCTR_CP",
> + "countable_type": "a8xx_cp_perfcounter_select"
> + },
> + {
> + "name": "RBBM",
> + "num": 4,
> + "select": "RBBM_PERFCTR_RBBM_SEL",
> + "slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ],
> + "counter": "RBBM_PERFCTR_RBBM",
> + "countable_type": "a8xx_rbbm_perfcounter_select"
> + },
> + {
> + "name": "PC",
> + "pipe": "BR",
> + "num": 8,
> + "select": "PC_PERFCTR_PC_SEL",
> + "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
> + "counter": "RBBM_PERFCTR_PC",
> + "countable_type": "a8xx_pc_perfcounter_select"
> + },
> + {
> + "name": "VFD",
> + "pipe": "BR",
> + "num": 8,
> + "select": "VFD_PERFCTR_VFD_SEL",
> + "counter": "RBBM_PERFCTR_VFD",
> + "countable_type": "a8xx_vfd_perfcounter_select"
> + },
> + {
> + "name": "HLSQ",
> + "pipe": "BR",
> + "num": 6,
> + "select": "SP_PERFCTR_HLSQ_SEL",
> + "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
> + "counter": "RBBM_PERFCTR_HLSQ",
> + "countable_type": "a8xx_hlsq_perfcounter_select"
> + },
> + {
> + "name": "VPC",
> + "pipe": "BR",
> + "num": 6,
> + "select": "VPC_PERFCTR_VPC_SEL",
> + "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
> + "counter": "RBBM_PERFCTR_VPC",
> + "countable_type": "a8xx_vpc_perfcounter_select"
> + },
> + {
> + "name": "TSE",
> + "pipe": "BR",
> + "num": 4,
> + "select": "GRAS_PERFCTR_TSE_SEL",
> + "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
> + "counter": "RBBM_PERFCTR_TSE",
> + "countable_type": "a8xx_tse_perfcounter_select"
> + },
> + {
> + "name": "RAS",
> + "pipe": "BR",
> + "num": 4,
> + "select": "GRAS_PERFCTR_RAS_SEL",
> + "counter": "RBBM_PERFCTR_RAS",
> + "countable_type": "a8xx_ras_perfcounter_select"
> + },
> + {
> + "name": "UCHE",
> + "num": 12,
"num": 24,
> + "select": "UCHE_PERFCTR_UCHE_SEL",
> + "counter": "RBBM_PERFCTR_UCHE",
> + "countable_type": "a8xx_uche_perfcounter_select"
> + },
> + {
> + "name": "TP",
> + "pipe": "BR",
> + "num": 12,
> + "select": "TPL1_PERFCTR_TP_SEL",
> + "counter": "RBBM_PERFCTR_TP",
> + "countable_type": "a8xx_tp_perfcounter_select"
> + },
> + {
> + "name": "SP",
> + "pipe": "BR",
> + "num": 24,
> + "select": "SP_PERFCTR_SP_SEL",
> + "counter": "RBBM_PERFCTR_SP",
> + "countable_type": "a8xx_sp_perfcounter_select"
> + },
> + {
> + "name": "RB",
> + "pipe": "BR",
> + "num": 8,
> + "select": "RB_PERFCTR_RB_SEL",
> + "counter": "RBBM_PERFCTR_RB",
> + "countable_type": "a8xx_rb_perfcounter_select"
> + },
> + {
> + "name": "VSC",
> + "num": 2,
> + "select": "VSC_PERFCTR_VSC_SEL",
> + "counter": "RBBM_PERFCTR_VSC",
> + "countable_type": "a8xx_vsc_perfcounter_select"
> + },
> + {
> + "name": "CCU",
> + "pipe": "BR",
> + "num": 5,
> + "select": "RB_PERFCTR_CCU_SEL",
> + "counter": "RBBM_PERFCTR_CCU",
> + "countable_type": "a8xx_ccu_perfcounter_select"
> + },
> + {
> + "name": "LRZ",
> + "pipe": "BR",
> + "num": 4,
> + "select": "GRAS_PERFCTR_LRZ_SEL",
> + "counter": "RBBM_PERFCTR_LRZ",
> + "countable_type": "a8xx_lrz_perfcounter_select"
> + },
> + {
> + "name": "CMP",
"pipe": "BR",
-Akhil
next prev parent reply other threads:[~2026-05-20 8:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-18 19:06 [PATCH v7 00/16] drm/msm: Add PERFCNTR_CONFIG ioctl Rob Clark
2026-05-18 19:06 ` [PATCH v7 01/16] drm/msm: Remove obsolete perf infrastructure Rob Clark
2026-05-18 19:06 ` [PATCH v7 02/16] drm/msm: Allow CAP_PERFMON for setting SYSPROF Rob Clark
2026-05-18 19:06 ` [PATCH v7 03/16] drm/msm/adreno: Sync registers from mesa Rob Clark
2026-05-18 19:06 ` [PATCH v7 04/16] drm/msm/registers: Sync gen_header.py " Rob Clark
2026-05-18 19:06 ` [PATCH v7 05/16] drm/msm/registers: Add perfcntr json Rob Clark
2026-05-20 8:36 ` Akhil P Oommen [this message]
2026-05-20 12:30 ` Rob Clark
2026-05-20 13:47 ` Rob Clark
2026-05-18 19:06 ` [PATCH v7 06/16] drm/msm: Add a6xx+ perfcntr tables Rob Clark
2026-05-18 19:06 ` [PATCH v7 07/16] drm/msm: Add sysprof accessors Rob Clark
2026-05-18 19:06 ` [PATCH v7 08/16] drm/msm/a6xx: Add yield & flush helper Rob Clark
2026-05-18 19:06 ` [PATCH v7 09/16] drm/msm: Add per-context perfcntr state Rob Clark
2026-05-18 19:06 ` [PATCH v7 10/16] drm/msm: Add basic perfcntr infrastructure Rob Clark
2026-05-18 19:06 ` [PATCH v7 11/16] drm/msm/a6xx+: Add support to configure perfcntrs Rob Clark
2026-05-18 19:06 ` [PATCH v7 12/16] drm/msm/a8xx: Add perfcntr flush sequence Rob Clark
2026-05-18 19:06 ` [PATCH v7 13/16] drm/msm: Add PERFCNTR_CONFIG ioctl Rob Clark
2026-05-18 19:06 ` [PATCH v7 14/16] drm/msm/a6xx: Increase pwrup_reglist size Rob Clark
2026-05-18 19:06 ` [PATCH v7 15/16] drm/msm/a6xx: Append SEL regs to dyn pwrup reglist Rob Clark
2026-05-20 8:39 ` Akhil P Oommen
2026-05-18 19:06 ` [PATCH v7 16/16] drm/msm/a6xx: Allow IFPC with perfcntr stream Rob Clark
2026-05-20 8:44 ` [PATCH v7 00/16] drm/msm: Add PERFCNTR_CONFIG ioctl Akhil P Oommen
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