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From: Michal Wilczynski <m.wilczynski@samsung.com>
To: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Cc: Vinod Koul <vkoul@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
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	Icenowy Zheng <zhengxingda@iscas.ac.cn>
Subject: Re: [PATCH v3 14/19] drm/bridge: starfive: Add JH7110 HDMI controller driver
Date: Mon, 14 Sep 2026 23:48:06 +0200	[thread overview]
Message-ID: <b4c80c88-9235-4ad0-bc23-53dddddfadb3@samsung.com> (raw)
In-Reply-To: <15741677-7f2c-4190-b77f-a496643593c6@rock-chips.com>



On 9/7/26 05:51, Chaoyi Chen wrote:
> Hello Michal,
> 
> On 9/4/2026 9:27 PM, Michal Wilczynski wrote:
>> Add the HDMI controller (bridge) driver for the StarFive JH7110.
>>
>> This driver binds to the starfive,jh7110-inno-hdmi-controller node.
>> It gets its shared regmap from its parent and its register access,
>> module and bus clocks from voutcrg. It consumes the pixel clock and the
>> PHY from its hdmi_phy sibling.
>>
>> The driver calls the generic inno_hdmi_probe function and passes the
>> shared regmap to it, registering as a DRM bridge. The .enable hook is
>> responsible for setting the PHY's pixel clock rate via clk_set_rate()
>> and powering on the PHY via phy_power_on().
>>
>> The DC8200 has two panels, each exposing a DP and a DPI interface, and a
>> mux in the video output system controller picks which of them drives the
>> HDMI transmitter. Program that mux from the port graph rather than
>> relying on whatever the bootloader left behind, taking the panel from the
>> remote port number and the interface from the remote endpoint number.
>>
>> The generic driver holds the clock it looks up as the register access
>> clock enabled for its lifetime, and derives the DDC divider from that
>> clock's rate, so point it at the system clock. Naming the pixel clock
>> there instead would keep the PHY pre-PLL powered from probe onwards and
>> size the divider from the wrong rate.
>>
>> The PHY can only generate the discrete set of pixel clocks described by
>> its pre-PLL table, so .mode_valid rejects any mode clk_round_rate()
>> cannot satisfy. Without it such a mode would be advertised to userspace
>> and the modeset would appear to succeed while the display stayed blank.
>>
>> .enable returns early when the rate is unsupported or the PHY fails to
>> power on, so track whether the pixel clock was actually enabled and let
>> .disable tear down only what was brought up, otherwise the clock
>> refcount underflows.
>>
>> The clocks and the reset are torn down through devm rather than from
>> .remove, so that they outlive the bridge that inno_hdmi_probe() adds with
>> devm_drm_bridge_add(). Releasing them in .remove runs before devres
>> unwinds and would leave the bridge registered with its clocks already
>> gated.
>>
>> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
>> ---
>>  drivers/gpu/drm/bridge/Kconfig            |  11 ++
>>  drivers/gpu/drm/bridge/Makefile           |   1 +
>>  drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 318 ++++++++++++++++++++++++++++++
>>  3 files changed, 330 insertions(+)
>>

[snip]

>> +static enum drm_mode_status
>> +inno_hdmi_starfive_mode_valid(struct device *dev,
>> +			      const struct drm_display_mode *mode)
>> +{
>> +	struct stf_inno_hdmi_controller *ctrl = dev_get_drvdata(dev);
>> +	unsigned long pixelclk = mode->clock * 1000;
>> +	long rounded;
>> +
>> +	/*
>> +	 * The PHY can only generate the discrete set of pixel clocks described
>> +	 * by its pre-PLL table, and clk_round_rate() fails for anything else.
>> +	 * Reject those modes here: without this the modeset would appear to
>> +	 * succeed while the PHY never produces a signal.
>> +	 */
>> +	rounded = clk_round_rate(ctrl->clks[CLK_PCLK].clk, pixelclk);
>> +	if (rounded < 0 || rounded != pixelclk)
>> +		return MODE_NOCLOCK;
>> +
> 
> Using "if (rounded != pixelclk)" would be ok.

Thanks will fix.

> 
>> +	return MODE_OK;
>> +}
>> +

[snip]

>> +/*
>> + * The DC8200 has two panels, each exposing a DP and a DPI interface, and a mux
>> + * in dom_vout_syscon picks which of them drives the HDMI transmitter. Derive
>> + * the mux setting from the port graph: the remote port number selects the
>> + * DC8200 panel, and the remote endpoint number the interface on that panel
>> + * (0 for DPI, 1 for DP). Both drive 8-bit RGB, the only format this driver
>> + * currently produces.
>> + */
>> +static int stf_inno_hdmi_setup_mux(struct device *dev)
>> +{
>> +	struct device_node *ep, *remote;
> 
> Using "struct device_node *ep __free(device_node)" can help you simplify
> the processing of resource release.
> 

Sure, thanks !

> 

Best regards,
-- 
Michal Wilczynski <m.wilczynski@samsung.com>


  reply	other threads:[~2026-09-14 21:48 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260904132708eucas1p1adfa26ef0fe5109eca63a3aeadf74915@eucas1p1.samsung.com>
2026-09-04 13:27 ` [PATCH v3 00/19] drm: starfive: jh7110: Enable display subsystem Michal Wilczynski
     [not found]   ` <CGME20260904132710eucas1p276bacb1cda0a62d7f29066bd66660fea@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 01/19] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy Michal Wilczynski
     [not found]   ` <CGME20260904132712eucas1p167f9527c4728af56f811d06832b43c36@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 02/19] dt-bindings: display: bridge: Add starfive,jh7110-inno-hdmi-controller Michal Wilczynski
     [not found]   ` <CGME20260904132714eucas1p1ddf12edea05cdeda7969f229ca90bd26@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 03/19] dt-bindings: mfd: Add starfive,jh7110-hdmi-subsystem Michal Wilczynski
     [not found]   ` <CGME20260904132716eucas1p2d093509db255e62e6bd546e734f04e63@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 04/19] dt-bindings: soc: starfive: Add starfive,jh7110-vout-syscon Michal Wilczynski
2026-09-10  8:18       ` Krzysztof Kozlowski
2026-09-14 21:43         ` Michal Wilczynski
     [not found]   ` <CGME20260904132718eucas1p1b25abe6cd0562e47dfeb75f8877e47b0@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 05/19] dt-bindings: soc: starfive: Add starfive,jh7110-vout-subsystem Michal Wilczynski
2026-09-10  8:21       ` Krzysztof Kozlowski
     [not found]   ` <CGME20260904132719eucas1p1c900149ffa1b8771aca238e6441482ee@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 06/19] dt-bindings: display: verisilicon: Add starfive,jh7110-dc8200 Michal Wilczynski
2026-09-10  8:34       ` Krzysztof Kozlowski
2026-09-14 19:37         ` Michal Wilczynski
     [not found]   ` <CGME20260904132721eucas1p2e5f5bb9d907e641c4488908403b9d52f@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 07/19] drm/bridge: inno-hdmi: Split probe out of bind Michal Wilczynski
     [not found]   ` <CGME20260904132723eucas1p14cdff81f7ccdc02ec811179c5d401d69@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 08/19] drm/bridge: inno-hdmi: Allow the register map to come from a parent Michal Wilczynski
     [not found]   ` <CGME20260904132725eucas1p19c8f66b7844108641dec1d2c39989dd5@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 09/19] drm/bridge: inno-hdmi: Add .disable platform operation Michal Wilczynski
     [not found]   ` <CGME20260904132727eucas1p241a5ba1517b5c6a2efde7bb2fdebf299@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 10/19] drm/bridge: inno-hdmi: Add .mode_valid " Michal Wilczynski
     [not found]   ` <CGME20260904132729eucas1p1bd78eb90feaf90b6265c13fc7bf43ada@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 11/19] soc: starfive: Add jh7110-hdmi-subsystem driver Michal Wilczynski
2026-09-07  8:23       ` Uwe Kleine-König
2026-09-14 21:46         ` Michal Wilczynski
     [not found]   ` <CGME20260904132731eucas1p182c607567520f7c6f482a9c85ab64ece@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 12/19] soc: starfive: Add jh7110-vout-subsystem driver Michal Wilczynski
     [not found]   ` <CGME20260904132733eucas1p1a6529cb2ea97bc75c9cd190d1ba901c0@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 13/19] clk: starfive: jh7110-vout: Allow pixel clock rate propagation Michal Wilczynski
     [not found]   ` <CGME20260904132735eucas1p2c898afe4a4c6e957a7b9eedff321a6dc@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 14/19] drm/bridge: starfive: Add JH7110 HDMI controller driver Michal Wilczynski
2026-09-04 13:39       ` Icenowy Zheng
2026-09-14 15:47         ` Michal Wilczynski
2026-09-07  3:51       ` Chaoyi Chen
2026-09-14 21:48         ` Michal Wilczynski [this message]
     [not found]   ` <CGME20260904132737eucas1p240d02860355b180ff9c5e8e4c6941ec0@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 15/19] phy: Add common Innosilicon HDMI PHY helpers Michal Wilczynski
2026-09-07  3:16       ` Chaoyi Chen
     [not found]   ` <CGME20260904132739eucas1p223161c8aa461d6ad18786635ab3c9de4@eucas1p2.samsung.com>
2026-09-04 13:27     ` [PATCH v3 16/19] phy: rockchip: inno-hdmi: Use the common Innosilicon " Michal Wilczynski
2026-09-07  3:20       ` Chaoyi Chen
     [not found]   ` <CGME20260904132741eucas1p1a60fc27f22cb79ef94aeb637334124f2@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 17/19] phy: starfive: Add jh7110-inno-hdmi-phy driver Michal Wilczynski
     [not found]   ` <CGME20260904132743eucas1p1e02218d3fb38af95c3dd4bfa24904cab@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 18/19] riscv: dts: starfive: jh7110: Update DT for display subsystem Michal Wilczynski
2026-09-10  8:37       ` Krzysztof Kozlowski
2026-09-14 19:38         ` Michal Wilczynski
     [not found]   ` <CGME20260904132745eucas1p1cd078aae0c24302622db6e2e0f617c31@eucas1p1.samsung.com>
2026-09-04 13:27     ` [PATCH v3 19/19] MAINTAINERS: Add StarFive JH7110 display subsystem entry Michal Wilczynski
2026-09-04 15:13   ` [PATCH v3 00/19] drm: starfive: jh7110: Enable display subsystem Joshua Peisach
2026-09-14 21:02     ` Michal Wilczynski
2026-09-05  5:21   ` Maud Spierings
     [not found]     ` <CAAvaLCzU_-JdPHSSQS2HxGnrkRk+u_QOZ91SmxcC+nouubCtXA@mail.gmail.com>
2026-09-14 15:50       ` Michal Wilczynski

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