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([2a05:6e02:1041:c10:d521:838e:7c69:f457]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3e7607d7593sm2360205f8f.43.2025.09.11.05.55.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Sep 2025 05:55:01 -0700 (PDT) Message-ID: Date: Thu, 11 Sep 2025 14:55:00 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms To: Jonathan Cameron Cc: dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, robh@kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org, linux-iio@vger.kernel.org, s32@nxp.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com References: <20250910155759.75380-1-daniel.lezcano@linaro.org> <20250910155759.75380-3-daniel.lezcano@linaro.org> <20250910183212.6640e662@jic23-huawei> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <20250910183212.6640e662@jic23-huawei> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Jonathan, thanks for the review On 10/09/2025 19:32, Jonathan Cameron wrote: > On Wed, 10 Sep 2025 17:57:56 +0200 > Daniel Lezcano wrote: [ ... ] >> +/* Main Configuration Register */ >> +#define REG_ADC_MCR(__base) ((__base) + 0x00) > > I'm not really convinced these macros help over just having > readl(info->regs + NXP_SADC_MCR_REG); That is really a matter of taste :) I used to create this format in order to stick the macros with the debugfs register code which is not part of these changes. There is a similar format in drivers/clocksource/timer-nxp-stm.c or driver/thermal/mediatek/lvts.c IMHO is less prone to error than base + REG all around the code. Do you want me to convert all the macros to info->__base + MACRO ? [ ... ] >> +static const struct iio_chan_spec nxp_sar_adc_iio_channels[] = { >> + ADC_CHAN(0, IIO_VOLTAGE), >> + ADC_CHAN(1, IIO_VOLTAGE), >> + ADC_CHAN(2, IIO_VOLTAGE), >> + ADC_CHAN(3, IIO_VOLTAGE), >> + ADC_CHAN(4, IIO_VOLTAGE), >> + ADC_CHAN(5, IIO_VOLTAGE), >> + ADC_CHAN(6, IIO_VOLTAGE), >> + ADC_CHAN(7, IIO_VOLTAGE), >> + IIO_CHAN_SOFT_TIMESTAMP(32), > > Whilst we only insist on monotonic numbering, putting it all the way down > at 32 seems excessive. Why not 8? Perhaps a comment if this is to avoid > moving it for some future feature. The ADC has 8 channels for external acquisition however others channels 8->31 are described as reserved. They may evolve in the future to more channels. That is probably the reason why 32 is used here. [ ... ] >> + indio_dev->name = dev_name(dev); > > This should be the 'part number'. That is a little ill defined > for a SoC integrated ADC, but generally not what we get from dev_name() > on the platform_device. Sorry, I don't get the comment. If I refer to the different drivers there is not consistency with the iio_dev->name. rtq6056.c: indio_dev->name = "rtq6056"; rzg2l_adc.c: indio_dev->name = DRIVER_NAME; sc27xx_adc.c: indio_dev->name = dev_name(dev); mt6359-auxadc.c: indio_dev->name = adc_dev->chip_info->model_name; mcp3911.c: indio_dev->name = spi_get_device_id(spi)->name; Are you suggesting to use the compatible part number ? indio->name = "s32g2-sar-adc"; -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog