From: Shuai Xue <xueshuai@linux.alibaba.com>
To: Nicolin Chen <nicolinc@nvidia.com>,
jgg@nvidia.com, will@kernel.org, robin.murphy@arm.com
Cc: joro@8bytes.org, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
skolothumtho@nvidia.com, praan@google.com
Subject: Re: [PATCH rc v2 2/4] iommu/arm-smmu-v3: Ignore STE MEV when computing the update sequence
Date: Mon, 8 Dec 2025 10:33:23 +0800 [thread overview]
Message-ID: <b4d96532-09b5-4162-8d9e-c41ca2baba0b@linux.alibaba.com> (raw)
In-Reply-To: <08fd4d48e684732ad58064f690195f31a64979c4.1765140287.git.nicolinc@nvidia.com>
在 2025/12/8 04:49, Nicolin Chen 写道:
> From: Jason Gunthorpe <jgg@nvidia.com>
>
> Nested CD tables set the MEV bit to try to reduce multi-fault spamming on
> the hypervisor. Since MEV is in STE word 1 this causes a breaking update
> sequence that is not required and impacts real workloads.
>
> For the purposes of STE updates the value of MEV doesn't matter, if it is
> set/cleared early or late it just results in a change to the fault reports
> that must be supported by the kernel anyhow. The spec says:
>
> Note: Software must expect, and be able to deal with, coalesced fault
> records even when MEV == 0.
>
> So ignore MEV when computing the update sequence to avoid creating a
> breaking update.
>
> Fixes: da0c56520e88 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations")
> Cc: stable@vger.kernel.org
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index e22c0890041b..3e161d8298d9 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -1085,6 +1085,16 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_used);
> VISIBLE_IF_KUNIT
> void arm_smmu_get_ste_ignored(__le64 *ignored_bits)
> {
> + /*
> + * MEV does not meaningfully impact the operation of the HW, it only
> + * changes how many fault events are generated, thus we can ignore it
> + * when computing the ordering. The spec notes the device can act like
> + * MEV=1 anyhow:
> + *
> + * Note: Software must expect, and be able to deal with, coalesced
> + * fault records even when MEV == 0.
> + */
> + ignored_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV);
> }
> EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_ignored);
>
Reviewed-by: Shuai Xue <xueshuai@linux.alibaba.com>
Thanks.
Shuai
next prev parent reply other threads:[~2025-12-08 2:33 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-07 20:49 [PATCH rc v2 0/4] iommu/arm-smmu-v3: Fix hitless STE update in nesting cases Nicolin Chen
2025-12-07 20:49 ` [PATCH rc v2 1/4] iommu/arm-smmu-v3: Add ignored bits to fix STE update sequence Nicolin Chen
2025-12-08 2:33 ` Shuai Xue
2025-12-07 20:49 ` [PATCH rc v2 2/4] iommu/arm-smmu-v3: Ignore STE MEV when computing the " Nicolin Chen
2025-12-08 2:33 ` Shuai Xue [this message]
2025-12-07 20:49 ` [PATCH rc v2 3/4] iommu/arm-smmu-v3: Ignore STE EATS " Nicolin Chen
2025-12-08 2:33 ` Shuai Xue
2025-12-07 20:49 ` [PATCH rc v2 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Nicolin Chen
2025-12-08 3:43 ` Shuai Xue
2025-12-09 21:04 ` Nicolin Chen
2025-12-10 1:53 ` Shuai Xue
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