From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DD8BA383C8D for ; Fri, 19 Jun 2026 15:54:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781884473; cv=none; b=FObGYBSTxTqgLmlwNhErHuoB1ULqo4G6vwLK9RNdQ4wKeN9oBR5BdBr83rBRpgZ7Us1swVj5EloyxcQDE5FE6Lq5bn30rixw+sJ5KXbTc6/++Znl6VvZT58ITAZbbl7BmOz+8svBSSmtp4VPcogUvnzvMfLFBxOnXvdXZs39sWI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781884473; c=relaxed/simple; bh=ScdVpAAEUlglKYhgblarj/aY1vlSzcXqZZn90JqHVRM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=HhBHux/K+7A2oWoj379hVrd6Hy19H09PZ6YYOAjJyxPqBFK0nsL5mLOPynC12GiYE0YAg/02qxDFNjnqvA6bgnDB/hABOsiA8DPBj2bppsLcz8hUZiBvKI+orv3J4oQCL61scmjH+vpOcJ3aHo2qa8ZyN4576pp8shgboFqCsXY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=rR92kd0g; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="rR92kd0g" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 707A627DC; Fri, 19 Jun 2026 08:54:22 -0700 (PDT) Received: from [10.57.95.87] (unknown [10.57.95.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 058763F763; Fri, 19 Jun 2026 08:54:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1781884467; bh=ScdVpAAEUlglKYhgblarj/aY1vlSzcXqZZn90JqHVRM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=rR92kd0glh5jwf0W8S7Wqiqwjztn+fRhmKmRwPc3S+2HAgi1boPfF3AuGtiPFL1vX uOMimRzA2/2zRo1kD9pc4PEivvcaAc6rkJYFahOhX1yleErXUOnHOwRpLaslbE3cSz sBuDw7MRB76zlX9hagYVCosKb/Wmf3PfE0eTjlS8= Message-ID: Date: Fri, 19 Jun 2026 16:54:22 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu Content-Language: en-GB To: Will Deacon Cc: Linu Cherian , Catalin Marinas , Kevin Brodsky , Anshuman Khandual , Yang Shi , Mark Rutland , Huang Ying , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, shameerali.kolothum.thodi@huawei.com References: <20260523134710.3827956-1-linu.cherian@arm.com> <4aa78619-5a79-4fd0-aaac-a990b8c3fd05@arm.com> From: Ryan Roberts In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 19/06/2026 16:34, Will Deacon wrote: > On Mon, Jun 15, 2026 at 04:41:04PM +0100, Ryan Roberts wrote: >> On 15/06/2026 15:43, Will Deacon wrote: >>> On Mon, Jun 15, 2026 at 12:21:19PM +0100, Ryan Roberts wrote: >>>>>> + self = smp_processor_id(); >>>>>> + >>>>>> + /* >>>>>> + * The load of mm->context.active_cpu must not be reordered before the >>>>>> + * store to the pgtable that necessitated this flush. This ensures that >>>>>> + * if the value read is our cpu id, then no other cpu can have seen the >>>>>> + * old pgtable value and therefore does not need this old value to be >>>>>> + * flushed from its tlb. But we don't want to upgrade the dsb(ishst), >>>>>> + * needed to make the pgtable updates visible to the walker, to a >>>>>> + * dsb(ish) by default. So speculatively load without a barrier and if >>>>>> + * it indicates our cpu id, then upgrade the barrier and re-load. >>>>>> + */ >>>>>> + active = READ_ONCE(mm->context.active_cpu); >>>>>> + if (active == self) { >>>>>> + dsb(ish); >>>>>> + active = READ_ONCE(mm->context.active_cpu); >>>>>> + } else { >>>>>> + dsb(ishst); >>>>>> + } >>>>> >>>>> Why can't you just do: >>>>> >>>>> dsb(ishst); >>>>> active = READ_ONCE(mm->context.active_cpu); >>>>> >>>>> ? >>>> >>>> Prior to this optimization, we always issued a dsb(ishst) here. Catalin >>>> suggested the same simplification against the RFC. I believe Linu tried it but >>>> saw regressions; Hopefully Linu can provide the details. >>> >>> I don't follow... >>> >>> The old code always did dsb(ishst). The proposed code here does either >>> dsb(ish) or dsb(ishst). How can that possibly be faster? >> >> Ugh, sorry - I read your suggestion as unconditionally issuing a dsb(ish). >> >> Ignore my previous answer, and now I'll demonstrate my total lack of >> understanding of barriers instead... >> >> As the comment says, "The load of mm->context.active_cpu must not be reordered >> before the store to the pgtable that necessitated this flush". I thought that a >> dsb(ishst) would only provide ordering between stores. Don't we need the >> dsb(ish) to prevent the load from being reordered before the store? > > dsb(ishst) orders prior stores -> everything later. That's why it works > today for ordered a PTE write before a TLBI (which isn't a store). Ahh, that simplifies things then! > > Will