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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by MWH0EPF000A6732.mail.protection.outlook.com (10.167.249.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Thu, 4 Jun 2026 03:56:24 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Wed, 3 Jun 2026 22:56:24 -0500 Received: from [10.136.33.4] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Wed, 3 Jun 2026 22:56:21 -0500 Message-ID: Date: Thu, 4 Jun 2026 09:26:20 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] cpufreq/amd-pstate: Fix EPP initialization for shared memory systems To: Mario Limonciello , Marco Scardovi CC: , , , , , , , References: <4cb9459c-f471-478a-9670-58d898619f45@amd.com> <20260603120121.25772-1-scardracs@disroot.org> <20260603120121.25772-2-scardracs@disroot.org> <2e3a5f9a-69fe-4790-8b8b-2d1622977a2f@amd.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <2e3a5f9a-69fe-4790-8b8b-2d1622977a2f@amd.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YEm2Cl8NCCFTq+POzNomcs43hWFGAvsGZo9ssNYLAAQoajX5EZv/krRQjWHN/B6HCUEKnyfwoAZJbK5zverLZOg8ZZqxmqJdnis+ZTH4xwn21imHTR8vzDyZF+M1gQ3+sbFkzYq+sqCDFFTgsuM61HFOSM8CCopw8DmuUylxtYw9c4efXQ6GsTK83Vr0ryAr0cnhQBm5y4vArUeTtEOKSzIDn2lbl3FlXtYAPZPSHTF5qO7//LrgzmIrCgkc/WEYSgkDBsRgnpf4JrqEiWXep0wK6lKyGRaQRSYRdqG4PIA7BkaFKFIF0B5ekf1i9sfYQOds1mjTONHjwphN3uCGbCtThlnhbhDUzG9/6k7Nlob0WIULwNBIivSBNDGTOCNA6Ucp3tFIGWbHo7q1ODeCHgXc0zTH2hkH+QSd3ETjpwumOmMClYNeuoJnmfNzt5M6 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jun 2026 03:56:24.7417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8b40d831-adac-4b76-114e-08dec1ed3f66 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6732.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8864 Hello Mario, On 6/4/2026 12:23 AM, Mario Limonciello wrote: >> --- a/drivers/cpufreq/amd-pstate.h >> +++ b/drivers/cpufreq/amd-pstate.h >> @@ -128,6 +128,8 @@ struct amd_cpudata { >>       u8    epp_default_dc; >>       bool    dynamic_epp; >>       bool    raw_epp; >> +    /* Indicates that EPP has been successfully programmed at least once since boot. */ >> +    bool    epp_hw_programmed; >>       struct notifier_block power_nb; >>         /* platform profile */ > > I'm having a hard time following why this is needed.  Let me explain my chain of thought. > > We start at amd_pstate_epp_cpu_init(). > * cpudata (and thus cppc_req_cached) is initalized to 0 via kzalloc() >    - On a server we initialize "epp_default" via a lookup to the HW (amd_pstate_get_epp). >    - On a non-server we initialize "epp_default" to 0x80. > * we call amd_pstate_set_epp() with epp_deafult as the argument. > > Now in the shared mem backend (shmem_set_epp) we do a lookup of epp_cached and it should be 0.  We do a comparison of the argument sent to the function, and this should be 0x80. > > So how do we get into a case that amd_pstate_set_epp() is actually called with 0? This was the path I traced yesterday considering amd_dynamic_epp enabled for a shared memory system that is plugged into the wall: amd_pstate_epp_cpu_init() cpudata->epp_default_ac = AMD_CPPC_EPP_PERFORMANCE; cpudata->epp_default_dc = AMD_CPPC_EPP_BALANCE_PERFORMANCE; cpudata->current_profile = PLATFORM_PROFILE_BALANCED; /* cpudata->cppc_req_cached has epp_cached as 0 */ amd_pstate_set_dynamic_epp(policy) epp = amd_pstate_get_balanced_epp(policy); /* returns cpudata->epp_default_ac which is EPP_PERFORMANCE */ amd_pstate_set_epp(policy, epp /* AMD_CPPC_EPP_PERFORMANCE */) if (epp == epp_cached) return; /* * Skips cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1) * where the last argument "enable" enables EPP via the * AUTO_SEL_ENABLE path. */ > > There are some trace points specifically for this purpose - you could confirm there really is such a call by using them at bootup (or by starting in passive and with a mode change to active at runtime). It should show up in the traces yes! > > Then we call amd_pstate_set_epp() with that epp_default value. I think this patch has some merit, although the second patch, I'm not too sure of. After some digging, it seems we always had AUTO_SEL_ENABLE and ENERGY_PERF right from the time CPPC was introduced (including Zen1 systems that had CPPC support). Marco, do you have actually have a system that neither has AUTO_SEL_ENABLE, nor ENERGY_PERF? Seems very unlikely a configuration like that made it out. -- Thanks and Regards, Prateek