From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754764AbdLOBsw (ORCPT ); Thu, 14 Dec 2017 20:48:52 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:23884 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754538AbdLOBsu (ORCPT ); Thu, 14 Dec 2017 20:48:50 -0500 Subject: Re: [PATCH v7 6/6] arm64: dts: meson-axg: switch uart_ao clock to CLK81 To: Jerome Brunet , Neil Armstrong , Kevin Hilman References: <20171211141348.22048-1-yixun.lan@amlogic.com> <20171211141348.22048-7-yixun.lan@amlogic.com> <1513270051.2261.11.camel@baylibre.com> CC: , Rob Herring , Mark Rutland , Michael Turquette , Stephen Boyd , Carlo Caione , Qiufang Dai , Jian Hu , , , , , From: Yixun Lan Message-ID: Date: Fri, 15 Dec 2017 09:49:11 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <1513270051.2261.11.camel@baylibre.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.20.164] X-ClientProxiedBy: mail-sh2.amlogic.com (10.18.11.6) To mail-sh2.amlogic.com (10.18.11.6) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/15/17 00:47, Jerome Brunet wrote: > On Mon, 2017-12-11 at 22:13 +0800, Yixun Lan wrote: >> Switch the uart_ao pclk to CLK81 since the clock driver is ready. >> Also move the clock info to the board.dts instead in the soc.dtsi. > > Same comment as for ethmac, is it really wise ? > Isn't the clock setup the same for the axg family ? > HI Jerome: yes, should be same for AXG family HI Kevin: could you take the patch [5/6]? then I just need to resend for this one Yixun