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Wed, 15 Apr 2026 14:17:54 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , Subject: [PATCH rc v2 3/5] iommu/arm-smmu-v3: Retain CR0_SMMUEN during kdump device reset Date: Wed, 15 Apr 2026 14:17:38 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000C6187:EE_|PH7PR12MB6739:EE_ X-MS-Office365-Filtering-Correlation-Id: 1057bdb9-7f28-445f-d77d-08de9b348048 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|36860700016|82310400026|22082099003|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: Yk/jRD9fPWzo0QLHwaQuOCHZlCjU0ffC+8fACjy7jvFK3Ch5NZBcxDlEl3hqIQ2hGPlVceY8sFWLzWvMOF6WyqUhfu2j7au42q2jwnCF0u6871V9n4JBTcJ17ODYHG4l/E6qF65qWx4HNw+sNsUQulaVALvD3/bmVzq3jL6q7pH5gEZjSMxmJ8kqI1LvILhXUL0nk4I8E1kQISbVjP4X2F5BcRH8Bh+AQr3mPT1ujHeyFE1Nd2RToGY7y8u705fiONHfh7FBPfK5kSUlVslbXqLjUprCTpCoCEsyhv8RYMYocJKJrtx53d8UQqflnhzayID6f81vXo/d0hpe/qqD5dGvDaLhPK8aZteZCjYzA/LcThZvtIQZkYoUzT+YHiH8QcBLmEgWHhYQnvUajLkw1D+ilP5YULCD/KChHrw/jEYTMJbCWYAWqPcqePAq7rHz9no+yBIydQ2BBFTsKrZNieZ9TiPbmZIHwWfnnhCIGMXPIKWRHe5FqZr0mxAZPKwDStndS2x+nf/9WUIzUfqPET2E+TVDoeWQjxA8zamKmMKYJhn8OOD440jAadRpfvbGaZTy3tVLHnP15qX2X3FH6rE3CKuNDDheVoDFz9NYnDTmIb09XwISarNsB4o4qzAtdLM8nasG5IjGgnRVay5/50gCO8QE+4EggqJ/lPATvfEWP1J+wLRxHHbjJca2CQJlgDQt8E02yU/OxuPyfZOTNAUl0MK7AILr61UHb8kTgOYgj4qf0SuSZyAsXl3bL8FABsOyzUQXsIF1D2PlSJByLQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(376014)(36860700016)(82310400026)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jb56BqMsD60YxZ9R7OV8rqMD+liiPr4yJxWeI+YNXFeS0zYdD81gR0ho+avnizCNM3FXsAzFqLdeXQGHFhVZ3ZiUHPvG209dVQpKGaOoEtD8KWjkwhZwUVKhwqDExaq+LD6CKIN7rdLtCp2d21fIS4S1ViQQNKlrmmrUBI+DjWn2rcp7InIjHodCgfjxpDIR+Gs46eGurk7lOWjVnit02iM+s3HQgbfFbTVjATTYYPOZ55mJkfSvvqN6/gjad9iSwtIt/2kXbjntNmfOGMH+wIotSxiDpbl8EgZQzaUfCceiXIkv1oHnJfZGJDylaq+gEC0DwGrzJVwZFFIaMizNxFpyPALRv7pBc31dN05o6mcYk1smojsZjA6uFHOIHyNaPIPtfJbeLmSqBwXHsTqONbrcB8r60usoZYE6sXUTWCApp9HFTkMN80oQzPlr1vMK X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2026 21:18:12.5035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1057bdb9-7f28-445f-d77d-08de9b348048 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000C6187.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6739 When ARM_SMMU_OPT_KDUMP is set, skip the GBPA/disable/CR1/CR2/STRTAB_BASE update sequence in arm_smmu_device_reset(). Those register writes are all CONSTRAINED UNPREDICTABLE while CR0_SMMUEN==1, so leaving them untouched lets in-flight DMA continue to be translated by the adopted stream table. Initialize 'enables' to 0 so it can carry CR0_SMMUEN in kdump case. Then, preserve that when enabling the command queue. Fixes: b63b3439b856 ("iommu/arm-smmu-v3: Abort all transactions if SMMU is enabled in kdump kernel") Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 29 +++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index d9d543eb8cecf..b2c34713bf9f2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4938,9 +4938,23 @@ static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) static int arm_smmu_device_reset(struct arm_smmu_device *smmu) { int ret; - u32 reg, enables; + u32 reg, enables = 0; struct arm_smmu_cmdq_ent cmd; + /* + * In a kdump case, retain CR0_SMMUEN to avoid transiently aborting in- + * flight DMA. According to spec, updating STRTAB_BASE, CR1, or CR2 when + * CR0_SMMUEN=1 is CONSTRAINED UNPREDICTABLE. Thus, skip those register + * updates and rely on the adopted stream table from the crashed kernel. + */ + if (smmu->options & ARM_SMMU_OPT_KDUMP) { + dev_info(smmu->dev, + "kdump: retaining SMMUEN for in-flight DMA\n"); + /* ARM_SMMU_OPT_KDUMP is only set when CR0_SMMUEN=1 */ + enables = CR0_SMMUEN; + goto reset_queues; + } + /* Clear CR0 and sync (disables SMMU and queue processing) */ reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); if (reg & CR0_SMMUEN) { @@ -4972,12 +4986,23 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Stream table */ arm_smmu_write_strtab(smmu); +reset_queues: + if (smmu->options & ARM_SMMU_OPT_KDUMP) { + /* Disable queues since arm_smmu_device_disable() was skipped */ + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { + dev_err(smmu->dev, "failed to disable queues\n"); + return ret; + } + } + /* Command queue */ writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); - enables = CR0_CMDQEN; + enables |= CR0_CMDQEN; ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); if (ret) { -- 2.43.0