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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-615a8fe7995sm22946026a12.36.2025.08.14.04.22.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Aug 2025 04:22:59 -0700 (PDT) Message-ID: Date: Thu, 14 Aug 2025 13:22:57 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20250725-topic-x1e80100-gpu-bwvote-v2-1-58d2fbb6a127@linaro.org> <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDEwNyBTYWx0ZWRfX6S3pDilKS+hM aG+sjZHEAsyxLclgX68lh6uQwUxK966Y0h+Rjoepwc4XMsCHcmJWC68pe191BXGUHxw+bpLpthF 1W/9ifBi6Iyo2ZzAWZdTjOzpgvhH7T+qXOKcvU+eeKM+FFIcXyWxxBltcOU+70SnwejaHGbIFc9 j/Rz0dgSgXRYRVPGmrFhzSPlB+8P704T4FQbwwVQeAgvtWwMqV8FRNGQ6hlwF7kTKHzvHQYMEzw fcQ/FlIv8VnqT1tPKS3MPq/oODWaaIiDNHMA9lOehJznDmDA05efW440TL6jhzR896gfIO/hmuD roa6XWiq9ySTxPT6RZ5RwZp/y34GUGw7a17JJMc5gEvkdSpvNOdwW2t0gefUi0bzXrQ34LMwMfX VuV9FNET X-Proofpoint-GUID: CDwGAZNLXT6PEPba0D7xUXyEzwcJGYjM X-Authority-Analysis: v=2.4 cv=A+1sP7WG c=1 sm=1 tr=0 ts=689dc715 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=w8v9NIqJ3aMQWT92luIA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: CDwGAZNLXT6PEPba0D7xUXyEzwcJGYjM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-13_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110107 On 8/14/25 1:21 PM, Konrad Dybcio wrote: > On 7/31/25 12:19 PM, Konrad Dybcio wrote: >> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along >>> the Frequency and Power Domain level, but by default we leave the >>> OPP core scale the interconnect ddr path. >>> >>> Declare the Bus Control Modules (BCMs) and the corresponding parameters >>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>> >>> Reviewed-by: Dmitry Baryshkov >>> Signed-off-by: Neil Armstrong >>> --- >>> Changes in v2: >>> - Used proper ACV perfmode bit/freq >>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-gpu-bwvote-v1-1-946619b0f73a@linaro.org >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>> .pwrup_reglist = &a7xx_pwrup_reglist, >>> .gmu_chipid = 0x7050001, >>> .gmu_cgc_mode = 0x00020202, >>> + .bcms = (const struct a6xx_bcm[]) { >>> + { .name = "SH0", .buswidth = 16 }, >>> + { .name = "MC0", .buswidth = 4 }, >>> + { >>> + .name = "ACV", >>> + .fixed = true, >>> + .perfmode = BIT(3), >>> + .perfmode_bw = 16500000, >> >> Reviewed-by: Konrad Dybcio > > Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) This is *very* platform-dependent, goes without saying.. I see BIT(2) is also valid for X1P4 Konrad