From: <Kelvin.Cao@microchip.com>
To: <vkoul@kernel.org>
Cc: <dmaengine@vger.kernel.org>, <George.Ge@microchip.com>,
<christophe.jaillet@wanadoo.fr>, <hch@infradead.org>,
<linux-kernel@vger.kernel.org>, <logang@deltatee.com>
Subject: Re: [PATCH v6 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver
Date: Mon, 23 Oct 2023 17:14:20 +0000 [thread overview]
Message-ID: <b5158f652d71790209626811eb0df2108384020b.camel@microchip.com> (raw)
In-Reply-To: <f6beb06cc707329923cc460545afd6cfe9fa065d.camel@microchip.com>
On Wed, 2023-10-11 at 16:36 +0000, Kelvin.Cao@microchip.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Wed, 2023-10-11 at 17:18 +0530, Vinod Koul wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you
> > know the content is safe
> >
> > On 10-10-23, 21:23, Kelvin.Cao@microchip.com wrote:
> > > On Mon, 2023-10-09 at 11:08 +0530, Vinod Koul wrote:
> >
> > > > > u64 size_to_transfer;
> > > >
> > > > Why cant the client driver write to doorbell, is there anything
> > > > which
> > > > prevents us from doing so?
> > >
> > > I think the potential challenge here for the client driver to
> > > ring
> > > db
> > > is that the client driver (host RC) is a different requester in
> > > the
> > > PCIe hierarchy compared to DMA EP, in which case PCIe ordering
> > > need
> > > to
> > > be considered.
> > >
> > > As PCIe ensures that reads don't pass writes, we can insert a
> > > read
> > > DMA
> > > operation with DMA_PREP_FENSE flag in between the two DMA writes
> > > (one
> > > for data transfer and one for notification) to ensure the
> > > ordering
> > > for
> > > the same requester DMA EP. I'm not sure if the RC could ensure
> > > the
> > > same
> > > ordering if the client driver issue MMIO write to db after the
> > > data
> > > DMA
> > > and read DMA completion, so that the consumer is guaranteed the
> > > transferred data is ready in memory when the db is triggered by
> > > the
> > > client MMIO write. I guess it's still doable with MMIO write but
> > > just
> > > some special consideration needed.
> >
> > Given that it is a single value, overhead of doing a new txn would
> > be
> > higher than a mmio write! I think that should be preferred
> >
> > --
>
> Ok. I'll remove the callback and come up with v7. Thank you Vinod for
> your comments.
>
Hi Vinod,
I've submitted v7 (title: [PATCH v7 0/1] Switchtec Switch DMA Engine
Driver) which removed the callback support for wimm as you suggested.
Please let me know if that looks good to you.
Thanks,
Kelvin
next prev parent reply other threads:[~2023-10-23 17:14 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-28 20:03 [PATCH v6 0/1] Switchtec Switch DMA Engine Driver Kelvin Cao
2023-07-28 20:03 ` [PATCH v6 1/1] dmaengine: switchtec-dma: Introduce Switchtec DMA engine PCI driver Kelvin Cao
2023-07-31 7:08 ` Christoph Hellwig
2023-07-31 23:07 ` Kelvin.Cao
2023-08-01 18:42 ` Vinod Koul
2023-08-03 3:15 ` Kelvin.Cao
2023-08-21 23:44 ` Kelvin.Cao
2023-10-05 18:35 ` Kelvin.Cao
2023-10-06 10:30 ` Vinod Koul
2023-10-06 22:34 ` Kelvin.Cao
2023-10-09 5:38 ` Vinod Koul
2023-10-10 21:23 ` Kelvin.Cao
2023-10-11 11:48 ` Vinod Koul
2023-10-11 16:36 ` Kelvin.Cao
2023-10-23 17:14 ` Kelvin.Cao [this message]
2023-12-12 17:53 ` Kelvin.Cao
2023-12-21 16:17 ` Vinod Koul
2023-07-31 15:49 ` [PATCH v6 0/1] Switchtec Switch DMA Engine Driver Logan Gunthorpe
2023-07-31 23:07 ` Kelvin.Cao
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