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X-CSE-ConnectionGUID: h0LHsCkBT4CgYr0Dc/PmEg== X-CSE-MsgGUID: Uw/SnIhPRy6Y0AN7ObDSKQ== X-IronPort-AV: E=McAfee;i="6800,10657,11465"; a="39838639" X-IronPort-AV: E=Sophos;i="6.16,241,1744095600"; d="scan'208";a="39838639" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 07:35:50 -0700 X-CSE-ConnectionGUID: 7PLTTM50R2+KvNynGxlxbQ== X-CSE-MsgGUID: vhpZlixnR3qEbKQKZotZMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,241,1744095600"; d="scan'208";a="179486859" Received: from msatwood-mobl.amr.corp.intel.com (HELO [10.125.108.25]) ([10.125.108.25]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jun 2025 07:35:49 -0700 Message-ID: Date: Mon, 16 Jun 2025 07:35:48 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 10/13] x86/mm: Simplify clear_page_* To: Ankur Arora , linux-kernel@vger.kernel.org, linux-mm@kvack.org, x86@kernel.org Cc: akpm@linux-foundation.org, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, mingo@redhat.com, mjguzik@gmail.com, luto@kernel.org, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org, tglx@linutronix.de, willy@infradead.org, jon.grimm@amd.com, bharata@amd.com, raghavendra.kt@amd.com, boris.ostrovsky@oracle.com, konrad.wilk@oracle.com References: <20250616052223.723982-1-ankur.a.arora@oracle.com> <20250616052223.723982-11-ankur.a.arora@oracle.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 6/15/25 22:22, Ankur Arora wrote: > clear_page_rep() and clear_page_erms() are wrappers around "REP; STOS" > variations. Inlining gets rid of the costly call/ret (for cases with > speculative execution related mitigations.) Could you elaborate a bit on which "speculative execution related mitigations" are so costly with these direct calls? > - kmsan_unpoison_memory(page, PAGE_SIZE); > - alternative_call_2(clear_page_orig, > - clear_page_rep, X86_FEATURE_REP_GOOD, > - clear_page_erms, X86_FEATURE_ERMS, > - "=D" (page), > - "D" (page), > - "cc", "memory", "rax", "rcx"); I've got to say, I don't dislike the old code. It's utterly clear from that code what's going on. It's arguable that it's not clear that the rep/erms variants are just using stosb vs. stosq, but the high level concept of "use a feature flag to switch between three implementations of clear page" is crystal clear. > + kmsan_unpoison_memory(page, len); > + asm volatile(ALTERNATIVE_2("call memzero_page_aligned_unrolled", > + "shrq $3, %%rcx; rep stosq", X86_FEATURE_REP_GOOD, > + "rep stosb", X86_FEATURE_ERMS) > + : "+c" (len), "+D" (page), ASM_CALL_CONSTRAINT > + : "a" (0) > + : "cc", "memory"); > } This is substantially less clear. It also doesn't even add comments to make up for the decreased clarity. > void copy_page(void *to, void *from); > diff --git a/arch/x86/lib/clear_page_64.S b/arch/x86/lib/clear_page_64.S > index a508e4a8c66a..27debe0c018c 100644 > --- a/arch/x86/lib/clear_page_64.S > +++ b/arch/x86/lib/clear_page_64.S > @@ -6,30 +6,15 @@ > #include > > /* > - * Most CPUs support enhanced REP MOVSB/STOSB instructions. It is > - * recommended to use this when possible and we do use them by default. > - * If enhanced REP MOVSB/STOSB is not available, try to use fast string. > - * Otherwise, use original. > + * Zero page aligned region. > + * %rdi - dest > + * %rcx - length > */ That comment was pretty useful, IMNHO. How about we add something like this above it? I think it explains the whole landscape, including the fact that X86_FEATURE_REP_GOOD is synthetic and X86_FEATURE_ERMS is not: Switch between three implementation of page clearing based on CPU capabilities: 1. memzero_page_aligned_unrolled(): the oldest, slowest and universally supported method. Uses a for loop (in assembly) to write a 64-byte cacheline on each loop. Each loop iteration writes to memory using 8x 8-byte MOV instructions. 2. "rep stosq": Really old CPUs had crummy REP implementations. Vendor CPU setup code sets 'REP_GOOD' on CPUs where REP can be trusted. The instruction writes 8 bytes per REP iteration but CPUs internally batch these together and do larger writes. 3. "rep stosb": CPUs that enumerate 'ERMS' have an improved STOS implementation that is less picky about alignment and where STOSB (1 byte at a time) is actually faster than STOSQ (8 bytes at a time).