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Wed, 15 Oct 2025 12:43:01 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , , Subject: [PATCH v3 1/7] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Date: Wed, 15 Oct 2025 12:42:46 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6730:EE_|PH0PR12MB7093:EE_ X-MS-Office365-Filtering-Correlation-Id: a3422b21-ed98-469f-5aeb-08de0c231756 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4gxgW6eAduGuNITHPjpXnOnSXYnUPQuqxo+IeFDr0c6szpTW/21rSN2iQfvM?= =?us-ascii?Q?NzI9Me5HS/pdyXqHj8WarEz5HssUquGP9TOS8yhfaUomJe+3ndVZulkWYOCe?= =?us-ascii?Q?jlXyiSLUwYHXzlsP2Vnq4CeMj+nfy4b5hjlHn5Bn479YHvhBgcYCZKhdSRV6?= =?us-ascii?Q?Ep1XO37KWgOjtKo/FbFs2MBuIfony8ZUTpW9b/cv3cU7OP+d6C2X8m+eLFDS?= =?us-ascii?Q?UrR6UHvyfoT8DNbRR7YTeN4ci3MPmF+v6zuz5KHJwEULNFCCJ4O9sJEppNz2?= =?us-ascii?Q?9mVwk4ou0oRr5z+kPXy1yW4M7Dk+lVjjyMdx4Y8XgKuQYTv6bLfnVNOu78MZ?= =?us-ascii?Q?CmXF11NNfSxMJPilWbvW2IuCdEnx2B/Xr5/0ZjhI85wACQeZyE0q6GDLlTnM?= =?us-ascii?Q?4Kl/eCeXDk41xAX+lI8sDXyOnnAGjh9cSMnDhLoOrTzRmSnDqjQtF5JJB8Ha?= =?us-ascii?Q?c0qlznx+mQzJn9hKIj/z5CTnju/jrmJ1rxMXmbmT+3uZNO6hQ0VXrM4I9ee+?= =?us-ascii?Q?0tFCXxkx+TE1tQCTusVc6mDcD/sXlMxLG8qRxg8MuuoEIn4UXrMPiKFC+Ytc?= =?us-ascii?Q?yVhbbePe9vZjawbamL/gaKwkW3RQyX+/UoHlFItDAHterMr1N8aqPuG0zIxW?= =?us-ascii?Q?zIqA+hdb+xgz+CD0tijLXJmU/UcX1agSGSXW4KLiSTfvqZRTjRNe1JdnV13v?= =?us-ascii?Q?aR4yfJpXbUBR2+qlxTo+5EKNcMAi9pTrVISWe1VJN13RliVEewGB9D514/Sq?= =?us-ascii?Q?6Gs08IBy74izoTQ+n+WIxGlbMUUt+RzuUd/IzHt6NoqwgI3bjXRw0XgWEjIR?= =?us-ascii?Q?cgo70IriExC7SgdALczYSc+P9SCveSiUPyYarGi73RGlhRqq5YLpIizBl9X+?= =?us-ascii?Q?3xnfIscjog5u8i7gtjo1SDP0Srz8TlI7wZ/ZGSNsK/5UVDHORsx29qCR4bUQ?= =?us-ascii?Q?lktQk4K85qJMuEqtsfnNd+buL4hBoGGQ24HoNAsccGChEx0wqz4SwGlULpEI?= =?us-ascii?Q?yMgoUdnjzX2eGTK6se7rc8o8/MgXc1ONDgkhGZgbVPHo5e84T8J6fEfEC93r?= =?us-ascii?Q?BePgrFqFl1Vj7ZitG453xRVFX51Jwo8XkIMuwoTWKRVLwTllr35fyX1bLjjo?= =?us-ascii?Q?VpeDS+D/GVBuKaOz+ffIxUuDBMGIgxLyTeuLbeOi4aIVx7PskTtxaoYoPxIE?= =?us-ascii?Q?rqGb6Y1C2tJU2/rzTVHieXsj5YglrO74h/9idXC8G2jdrGXAEvFsV4Bp6045?= =?us-ascii?Q?9HPjcgLD1YfgQHbU6vwVP/Pe0u/dckoZLGFNAF3LcyTvFaClEgOqTQzuzThw?= =?us-ascii?Q?lnJ2w7qiD5UcbkqsHB0lbTmmsbNnBspG/oeaosmFlCFe3vkF6zbVCSFtQOWF?= =?us-ascii?Q?gJdJ4H6S6+bbbXuCyS5NU8fNPg9Vr/BcG3ZWB8ZzVhzDRvXjd2ehBD3TuxsU?= =?us-ascii?Q?l5NJQtMQaQSNnNwZoqHkRXBzKSysREwridMpFAL/fycTMGer8ds5G5oLC6eC?= =?us-ascii?Q?RHajVFp+IJstUV9OQqQcQMtBB8IsxfOVXzbu8pcXuYu8QpLoJypkG2kn7xpn?= =?us-ascii?Q?K0sFXNprzKxVmyo7/50=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2025 19:43:18.6613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a3422b21-ed98-469f-5aeb-08de0c231756 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6730.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7093 Both the ARM_SMMU_DOMAIN_S1 case and the SVA case use ASID, requiring ASID based invalidation commands to flush the TLB. Define an ARM_SMMU_DOMAIN_SVA to make the SVA case clear to share the same path with the ARM_SMMU_DOMAIN_S1 case, which will be a part of the routine to build a new per-domain invalidation array. There is no function change. Suggested-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 3 files changed, 5 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ae23aacc38402..5c0b38595d209 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -858,6 +858,7 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, + ARM_SMMU_DOMAIN_SVA, }; struct arm_smmu_domain { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 59a480974d80f..6097f1f540d87 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -346,6 +346,7 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev, * ARM_SMMU_FEAT_RANGE_INV is present */ smmu_domain->domain.pgsize_bitmap = PAGE_SIZE; + smmu_domain->stage = ARM_SMMU_DOMAIN_SVA; smmu_domain->smmu = smmu; ret = xa_alloc(&arm_smmu_asid_xa, &asid, smmu_domain, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2a8b46b948f05..0312bb79f1247 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3064,6 +3064,9 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); break; + default: + WARN_ON(true); + break; } arm_smmu_attach_commit(&state); -- 2.43.0