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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: KL3BxXdjSyS1psYM-PMCcCeSrerLAwwZ X-Proofpoint-ORIG-GUID: KL3BxXdjSyS1psYM-PMCcCeSrerLAwwZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDA4OSBTYWx0ZWRfX/C4CvDED5TKD r3JtJBygx6s+4WeOiyc7n4Lm3hZm2vd3Z9+b/x0pfJH6RTvMDLrZlUlte8BjyTGHEGJ3QfbUTzL 6WygAppgPfS32MFS3G26rBqmlPHRz59dYR7CfJ0ZH23cHOgnSbvnvKp4xdM8MQzMG87mEejQiLr Vm4lvMJG3Sd2kD1EXMEpVUoZ5T50gn29kaPo+49gvePjhpbR2qU9B35dG3d5AociAOzIu3ZJeMf /5swlzPTjHV1elq86vT7LjZPMFkOD5Z9iLaUoPd93RVNi0Fa8lbUoIofLvwDdEDgsHp1diB6hg9 w2jGOTufQLI9MHCg+HP2+eSNaVIH5ho5k97Ga5NBKCBTYAFS8KOFZz2oBJFB2lAozgixMbTsP8q G++byCdYstVqeRs5//tcDzRH2z4sqFTPhStdvIdtYZNueN5+/9iiSHqrnaXNutiDOrLv6UMb X-Authority-Analysis: v=2.4 cv=QMFoRhLL c=1 sm=1 tr=0 ts=68651118 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=-s9buvLw_tBRhafl9uwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_01,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020089 On 7/2/2025 4:18 PM, Krzysztof Kozlowski wrote: > On 02/07/2025 12:46, Kathiravan Thirumoorthy wrote: >> On 7/2/2025 3:49 PM, Krzysztof Kozlowski wrote: >>> On 02/07/2025 12:17, Kathiravan Thirumoorthy wrote: >>>> IMEM is present in the Qualcomm's IPQ SoCs as well. Document the same. >>>> >>>> Signed-off-by: Kathiravan Thirumoorthy >>>> --- >>>> Documentation/devicetree/bindings/sram/qcom,imem.yaml | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>> Where is the changelog? This is not a v1. >> This is the v1. The series[1] I pointed out describes only for the >> IPQ5424 SoC. Since I have added few more SoCs, thought v1 is the >> appropriate numbering. >> >> [1] >> https://lore.kernel.org/linux-arm-msm/20250610-wdt_reset_reason-v5-0-2d2835160ab5@oss.qualcomm.com/ > But IPQ5424 is already there, so you reworked that patch. Okay, so this should be V6? > > >>>> diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> index 72d35e30c439ccf4901d937f838fe7c7a81f33b1..48e2f332e0e9fc9fa4147fa12d9c6c70a77fafda 100644 >>>> --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml >>>> @@ -18,6 +18,12 @@ properties: >>>> items: >>>> - enum: >>>> - qcom,apq8064-imem >>>> + - qcom,ipq8074-imem >>>> + - qcom,ipq6018-imem >>>> + - qcom,ipq5018-imem >>>> + - qcom,ipq9574-imem >>>> + - qcom,ipq5332-imem >>>> + - qcom,ipq5424-imem >>> Random order, no, follow existing style. This applies for every qcom >>> binding and you received such feedbacks in the past. >> Apologies — I arranged them based on the evolutionary order of SoCs. > Where is such ordering documented? How is it expressed in your internal > guideline for example? I made the mistake unintentionally and apologized for the same! > > Best regards, > Krzysztof