From: Jiri Slaby <jirislaby@kernel.org>
To: Rengarajan S <rengarajan.s@microchip.com>,
kumaravel.thiagarajan@microchip.com,
tharunkumar.pasumarthi@microchip.com, gregkh@linuxfoundation.org,
linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,
unglinuxdriver@microchip.com
Subject: Re: [PATCH v3 tty-next] 8250: microchip: pci1xxxx: Add PCIe Hot reset disable support for Rev C0 and later devices
Date: Mon, 28 Apr 2025 07:34:29 +0200 [thread overview]
Message-ID: <b56a3b02-3fd9-4461-b223-ba8b50d25157@kernel.org> (raw)
In-Reply-To: <20250425145500.29036-1-rengarajan.s@microchip.com>
On 25. 04. 25, 16:55, Rengarajan S wrote:
> Systems that issue PCIe hot reset requests during a suspend/resume
> cycle cause PCI1XXXX device revisions prior to C0 to get its UART
> configuration registers reset to hardware default values. This results
> in device inaccessibility and data transfer failures. Starting with
> Revision C0, support was added in the device hardware (via the Hot
> Reset Disable Bit) to allow resetting only the PCIe interface and its
> associated logic, but preserving the UART configuration during a hot
> reset. This patch enables the hot reset disable feature during suspend/
> resume for C0 and later revisions of the device.
>
> Signed-off-by: Rengarajan S <rengarajan.s@microchip.com>
My
Reviewed-by: Jiri Slaby <jirislaby@kernel.org>
still holds.
--
js
suse labs
prev parent reply other threads:[~2025-04-28 5:34 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-25 14:55 Rengarajan S
2025-04-28 5:34 ` Jiri Slaby [this message]
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