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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-af99604e648sm1369305966b.6.2025.08.13.02.42.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Aug 2025 02:42:46 -0700 (PDT) Message-ID: Date: Wed, 13 Aug 2025 11:42:44 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off To: Dikshita Agarwal , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong References: <20250813-sm8650-power-sequence-fix-v2-1-9ed0fc2c45cb@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250813-sm8650-power-sequence-fix-v2-1-9ed0fc2c45cb@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODExMDA3NCBTYWx0ZWRfX3MOGqAOzGnW1 MVYPlfmoBCNt+s7z9fI7EsHitaP3zcLc5uFOi4DzDjQcfydWxQvA40lNAwg2arys4WrOfOY81Bu Rvb/Yv4KdyAgIl7CjgbPI1nm6QMj6o8JkUUa1oo/r64RX2MWWVBoUV8N0cFsJpb0g5HNLHvV8ti 86Ra/pa4Ome8IPPrpNpP/t/OpYnlyB32aPAmN30cuVCNHnmEUCT3AKpA71XawgPFPsNe4hlKfs3 l0FX3lX9GrOdxJwtL2JTSssNpDQxH95dfi37aq6jTePr0VLHoCKCssJGSfodgfpgNiR4IrICwjN Txfci8eg1Uat+tHssK9aR76154xmXESiFDqu0Fsc+Z+/nJV3uyWor7QKmHTB0KjeE7AoX04m5Qw ZDmWswo8 X-Proofpoint-GUID: gu7wzhw4aF-Xj-dqJkZsM3_5yYd9BXGG X-Authority-Analysis: v=2.4 cv=TJFFS0la c=1 sm=1 tr=0 ts=689c5e18 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=DUSVluC6vKa5XdcSIjgA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: gu7wzhw4aF-Xj-dqJkZsM3_5yYd9BXGG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-12_08,2025-08-11_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508110074 On 8/13/25 9:53 AM, Dikshita Agarwal wrote: > Add the missing write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before > reading the LPI status register. Introduce a handshake loop to ensure > MNoC enters low power mode reliably during VPU3 hardware power-off with > timeout handling. > > Signed-off-by: Dikshita Agarwal > --- > Changes in v2: > - Restructured loop for readability (Jorge) > - Used defines for bits (Konrad, Jorge) > - Used udelay for short waits (Konrad) > - Link to v1: https://lore.kernel.org/r/20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com > > Please note that I have not added "Tested-by" tag from Neil in this update, > as the NOC handshake loop has been restructured. > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 30 +++++++++++++++++++++++++-- > 1 file changed, 28 insertions(+), 2 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..a621878f02f7196de29c9e290a6c5acea34eba8c 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -19,6 +19,9 @@ > #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > #define REQ_POWER_DOWN_PREP BIT(0) > #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > #define CORE_CLK_RUN 0x0 > > @@ -109,7 +112,9 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > > static void iris_vpu33_power_off_hardware(struct iris_core *core) > { > + bool handshake_done = false, handshake_busy = false; > u32 reg_val = 0, value, i; > + u32 count = 0; > int ret; > > if (iris_vpu3x_hw_power_collapsed(core)) > @@ -128,13 +133,34 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) > goto disable_power; > } > > + /* set MNoC to low power */ > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + > + do { > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS); > + > + handshake_done = value & NOC_LPI_STATUS_DONE; > + handshake_busy = value & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE); > + > + if (handshake_done || !handshake_busy) > + break; > + > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); I'm still concerned about the lack of readback here, since the writes aren't guaranteed to have a delay between them (from the VPU's perspective) > + > + udelay(15); > + > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + } while (++count < 1000); > + > + if (!handshake_done && handshake_busy) > + dev_err(core->dev, "LPI handshake timeout\n"); > + > ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, > reg_val, reg_val & BIT(0), 200, 2000); > if (ret) > goto disable_power; > > - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ > - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); > > writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, > core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); Just for context, is my understanding correct that we skip these writes when the handshake fails, because they cut power to the bus (which just failed to enter low power mode, meaning there's likely some data flowing through it)? Konrad