From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27DDC283FCE for ; Sun, 2 Aug 2026 16:16:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687403; cv=none; b=nlQG1kqbaM5KY+il3FP5bkoT5Z/UGsqhzOE+IeDSctF7C6iw7tWPlU8I0Ca2qjq1xjAbuVbKX9kaequiC1CH2yOgapKx0OUf89009F2zyP34Z8C7nKjxkbV30k6oebQsOug1GXffmq9c4BE1F6FkfhQsthzZcWpJDytiOLclCE0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687403; c=relaxed/simple; bh=Z2qIsPhZkIKYO1nTRVmjk/uIj+YgbH878R+xbFumj/g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=X1GDh6Kv6NExVRPdjQRpX7t3h/oXFFAtRtZa5xDWIyMjcEw9F8Hz3OXphuSX3FjduZAvd5R4M5fXFQriQlw3VzALyIwT4v/ysoDnp+PE9h7TyQ6wTPVD+rUs5gWgENObcx/ED7GRADuZ4inLr+T4QJKoCoce0udKB8nuDTmKqAA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Hhhih2bo; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Hhhih2bo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687401; x=1817223401; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z2qIsPhZkIKYO1nTRVmjk/uIj+YgbH878R+xbFumj/g=; b=Hhhih2boajCJCpXonXwhzqEsImx4qtERuPVjZsGGgWe3lVViHdNXp9ci m2ZyjNqSMFeO4t/t8IBxqXbf7mvb08myi/61UV1vSbFQgsYjBcsXIOyzA hxfmZQF28kYFQtOu2+W11EuMFT5VWyqQMKUG94YRE7lU7qVpGV3ycPCR7 fw4jA1wvnepSl/Gvui+sMFez3MsQBFUBSlxT2sEBPkR0QmEuokfXrkYNS TVaQGM3Z+utO4uzWPd4BWsm9F7Ckn5KUM9yZJ6ponsXLYsSv0t/15w1JA hGE8Y9WPCV2C9HLiNxETNvCHdGXHUrO4Mc77/BcRb4yAVmyNzouGqscUl g==; X-CSE-ConnectionGUID: mkZUPV1aRm+F4ZHoM0gUZw== X-CSE-MsgGUID: IkYAdMuTQhWBs2t5Z+cutA== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="86257945" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="86257945" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:16:40 -0700 X-CSE-ConnectionGUID: pT8Hx3l7TU+dmg9SbWo1/w== X-CSE-MsgGUID: j48dpHc9RwKd6HoAue9WTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="290950225" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa002.jf.intel.com with ESMTP; 02 Aug 2026 09:16:38 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 20/31] x86/resctrl: Rename msr_update to hw_update Date: Mon, 3 Aug 2026 00:06:56 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Prepare for the region aware RDT hardware update, and the region aware RDT touches the MMIO address rather than MSR registers. No functional change expected. Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/core.c | 28 ++++++++--------- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 38 +++++++++++------------ arch/x86/kernel/cpu/resctrl/internal.h | 8 ++--- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 14 ++++----- 4 files changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 1827e3ea5fee..0bde098db41e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -50,9 +50,9 @@ DEFINE_PER_CPU(struct resctrl_pqr_state, pqr_state); */ bool rdt_alloc_capable; -static void mba_wrmsr_intel(struct msr_param *m); -static void cat_wrmsr(struct msr_param *m); -static void mba_wrmsr_amd(struct msr_param *m); +static void mba_wrmsr_intel(struct hw_param *m); +static void cat_wrmsr(struct hw_param *m); +static void mba_wrmsr_amd(struct hw_param *m); #define ctrl_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.controls) #define mon_domain_init(id) LIST_HEAD_INIT(rdt_resources_all[id].r_resctrl.mon_domains) @@ -226,7 +226,7 @@ static __init bool __get_mem_config_intel(struct rdt_resource *r) hw_ctrl->r_ctrl.scalar.unit = RESCTRL_CTRL_UNIT_ALL; hw_ctrl->msr_base = MSR_IA32_MBA_THRTL_BASE; - hw_ctrl->msr_update = mba_wrmsr_intel; + hw_ctrl->hw_update = mba_wrmsr_intel; list_add(&hw_ctrl->r_ctrl.entry, &r->controls); r->alloc_capable = true; @@ -285,10 +285,10 @@ static __init bool __rdt_get_mem_config_amd(struct rdt_resource *r) if (r->rid == RDT_RESOURCE_MBA) { hw_ctrl->msr_base = MSR_IA32_MBA_BW_BASE; - hw_ctrl->msr_update = mba_wrmsr_amd; + hw_ctrl->hw_update = mba_wrmsr_amd; } else { /* r->rid == RDT_RESOURCE_SMBA */ hw_ctrl->msr_base = MSR_IA32_SMBA_BW_BASE; - hw_ctrl->msr_update = mba_wrmsr_amd; + hw_ctrl->hw_update = mba_wrmsr_amd; } list_add(&hw_ctrl->r_ctrl.entry, &r->controls); @@ -339,7 +339,7 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) } hw_ctrl->msr_base = idx == 1 ? MSR_IA32_L3_CBM_BASE: MSR_IA32_L2_CBM_BASE; - hw_ctrl->msr_update = cat_wrmsr; + hw_ctrl->hw_update = cat_wrmsr; list_add(&hw_ctrl->r_ctrl.entry, &r->controls); @@ -371,7 +371,7 @@ static void rdt_get_cdp_l2_config(void) rdt_get_cdp_config(RDT_RESOURCE_L2); } -static void mba_wrmsr_amd(struct msr_param *m) +static void mba_wrmsr_amd(struct hw_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct resctrl_hw_ctrl *hw_ctrl = resctrl_to_arch_ctrl(m->ctrl); @@ -395,7 +395,7 @@ static u32 delay_bw_map(unsigned long bw, struct rdt_resource *r) return MAX_MBA_BW; } -static void mba_wrmsr_intel(struct msr_param *m) +static void mba_wrmsr_intel(struct hw_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct resctrl_hw_ctrl *hw_ctrl = resctrl_to_arch_ctrl(m->ctrl); @@ -406,7 +406,7 @@ static void mba_wrmsr_intel(struct msr_param *m) wrmsrq(hw_ctrl->msr_base + i, delay_bw_map(hw_dom->ctrl_val[i], m->res)); } -static void cat_wrmsr(struct msr_param *m) +static void cat_wrmsr(struct hw_param *m) { struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(m->dom); struct resctrl_hw_ctrl *hw_ctrl = resctrl_to_arch_ctrl(m->ctrl); @@ -424,10 +424,10 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *r) void rdt_ctrl_update(void *arg) { struct resctrl_hw_ctrl *hw_ctrl; - struct msr_param *m = arg; + struct hw_param *m = arg; hw_ctrl = resctrl_to_arch_ctrl(m->ctrl); - hw_ctrl->msr_update(m); + hw_ctrl->hw_update(m); } static void setup_default_ctrlval(struct rdt_resource *r, struct resctrl_ctrl *ctrl, @@ -466,7 +466,7 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct resctrl_ctrl *ctr struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); struct resctrl_hw_ctrl *hw_ctrl = resctrl_to_arch_ctrl(ctrl); struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); - struct msr_param m; + struct hw_param m; u32 *dc; dc = kmalloc_array(hw_res->num_closid, sizeof(*hw_dom->ctrl_val), @@ -482,7 +482,7 @@ static int domain_setup_ctrlval(struct rdt_resource *r, struct resctrl_ctrl *ctr m.dom = d; m.low = 0; m.high = hw_res->num_closid; - hw_ctrl->msr_update(&m); + hw_ctrl->hw_update(&m); return 0; } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index ab765bca2ab5..1dd59d36e86c 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -26,19 +26,19 @@ int resctrl_arch_update_one(struct rdt_resource *r, struct resctrl_ctrl *ctrl, struct rdt_hw_ctrl_domain *hw_dom = resctrl_to_arch_ctrl_dom(d); struct resctrl_hw_ctrl *hw_ctrl = resctrl_to_arch_ctrl(ctrl); u32 idx = resctrl_get_config_index(closid, t); - struct msr_param msr_param; + struct hw_param hw_param; if (!cpumask_test_cpu(smp_processor_id(), &d->hdr.cpu_mask)) return -EINVAL; hw_dom->ctrl_val[idx] = cfg_val; - msr_param.res = r; - msr_param.ctrl = ctrl; - msr_param.dom = d; - msr_param.low = idx; - msr_param.high = idx + 1; - hw_ctrl->msr_update(&msr_param); + hw_param.res = r; + hw_param.ctrl = ctrl; + hw_param.dom = d; + hw_param.low = idx; + hw_param.high = idx + 1; + hw_ctrl->hw_update(&hw_param); return 0; } @@ -48,7 +48,7 @@ static void _resctrl_arch_update_domains(struct rdt_resource *r, { struct resctrl_staged_config *cfg; struct rdt_hw_ctrl_domain *hw_dom; - struct msr_param msr_param; + struct hw_param hw_param; struct rdt_ctrl_domain *d; enum resctrl_conf_type t; u32 idx; @@ -56,10 +56,10 @@ static void _resctrl_arch_update_domains(struct rdt_resource *r, /* Walking ctrl->domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); - msr_param.ctrl = ctrl; + hw_param.ctrl = ctrl; list_for_each_entry(d, &ctrl->domains, hdr.list) { hw_dom = resctrl_to_arch_ctrl_dom(d); - msr_param.res = NULL; + hw_param.res = NULL; for (t = 0; t < CDP_NUM_TYPES; t++) { cfg = &hw_dom->d_resctrl.staged_config[t]; if (!cfg->have_new_ctrl) @@ -70,18 +70,18 @@ static void _resctrl_arch_update_domains(struct rdt_resource *r, continue; hw_dom->ctrl_val[idx] = cfg->new_ctrl; - if (!msr_param.res) { - msr_param.low = idx; - msr_param.high = msr_param.low + 1; - msr_param.res = r; - msr_param.dom = d; + if (!hw_param.res) { + hw_param.low = idx; + hw_param.high = hw_param.low + 1; + hw_param.res = r; + hw_param.dom = d; } else { - msr_param.low = min(msr_param.low, idx); - msr_param.high = max(msr_param.high, idx + 1); + hw_param.low = min(hw_param.low, idx); + hw_param.high = max(hw_param.high, idx + 1); } } - if (msr_param.res) - smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &msr_param, 1); + if (hw_param.res) + smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &hw_param, 1); } } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index c48e8d4a62d5..ca9124e9aea5 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -88,14 +88,14 @@ struct arch_mbm_state { #define SDCIAE_ENABLE_BIT 1 /** - * struct msr_param - set a range of MSRs from a domain + * struct hw_param - set a range of registers (MSRs, etc) from a domain * @res: The resource to use * @ctrl: Properties of the control being updated * @dom: The domain to update * @low: Beginning index from base MSR * @high: End index */ -struct msr_param { +struct hw_param { struct rdt_resource *res; struct resctrl_ctrl *ctrl; struct rdt_ctrl_domain *dom; @@ -107,12 +107,12 @@ struct msr_param { * struct resctrl_hw_ctrl - Arch private properties of a resource control * @r_ctrl: Control properties exposed to resctrl file system * @msr_base: Base MSR address where control values should be programmed - * @msr_update: Function pointer to update control values + * @hw_update: Function pointer to update QOS hardware, MSRs, etc */ struct resctrl_hw_ctrl { struct resctrl_ctrl r_ctrl; unsigned int msr_base; - void (*msr_update)(struct msr_param *m); + void (*hw_update)(struct hw_param *m); }; static inline struct resctrl_hw_ctrl *resctrl_to_arch_ctrl(struct resctrl_ctrl *c) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 3048aa7b5c34..d06043bd27f8 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -234,7 +234,7 @@ void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct rdt_hw_ctrl_domain *hw_dom; - struct msr_param msr_param; + struct hw_param hw_param; struct resctrl_ctrl *ctrl; struct rdt_ctrl_domain *d; int i; @@ -242,9 +242,9 @@ void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) /* Walking ctrl->domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); - msr_param.res = r; - msr_param.low = 0; - msr_param.high = hw_res->num_closid; + hw_param.res = r; + hw_param.low = 0; + hw_param.high = hw_res->num_closid; /* * Disable resource control for this resource by setting all @@ -252,14 +252,14 @@ void resctrl_arch_reset_all_ctrls(struct rdt_resource *r) * Pick one CPU from each domain to update the MSRs below. */ for_each_resource_ctrl(ctrl, r) { - msr_param.ctrl = ctrl; + hw_param.ctrl = ctrl; list_for_each_entry(d, &ctrl->domains, hdr.list) { hw_dom = resctrl_to_arch_ctrl_dom(d); for (i = 0; i < hw_res->num_closid; i++) hw_dom->ctrl_val[i] = resctrl_get_default_ctrlval(ctrl); - msr_param.dom = d; - smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &msr_param, 1); + hw_param.dom = d; + smp_call_function_any(&d->hdr.cpu_mask, rdt_ctrl_update, &hw_param, 1); } } -- 2.43.0