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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2be249ed6a4sm1984701eec.11.2026.03.03.15.51.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Mar 2026 15:51:42 -0800 (PST) Message-ID: Date: Tue, 3 Mar 2026 15:51:41 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema To: Dmitry Baryshkov Cc: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Bryan O'Donoghue , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260226-x1e-csi2-phy-v3-0-11e608759410@linaro.org> <20260226-x1e-csi2-phy-v3-1-11e608759410@linaro.org> Content-Language: en-US From: Vijay Kumar Tumati In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=M85A6iws c=1 sm=1 tr=0 ts=69a77410 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=xyu7nF3SspGO5Dy-1yQA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: PhBwJV1NzrKvKYKtxoROW5hiWzyyvrOB X-Proofpoint-ORIG-GUID: PhBwJV1NzrKvKYKtxoROW5hiWzyyvrOB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzAzMDE5NiBTYWx0ZWRfX7w9wClC91Uef 445sgLb485hVdd/0xKxjPEI6aXZ0DZnXjAfdrl+piJ1O592wxeqYRbM3kZQhwK4Yn1iveYx+isP QJMFlUiesWwPCKl1k+Y4IVMf0V3Rz1tSyNnFuNtrZ7S+/Yc1wvR5m40tVisnFv4/oS0qd+Gu4Qe 8ujiHuE9BuJJ8wuMJNHxbi9bb+PDiHJpcx/Zz5x7lpiKCPjJuwRjnOJ3YkAOTdHL6apWve7YeJg 5zJ6+rvzJtys/TUEj1EzNjEBWoYWmstEXUId9I0PIfTzc07v/hUsU5dybz5kax0U7MRg3AoCCyF kpap91C2/QuPhFdJ/shywn0ytynyOjIGBl3pGOqhNH8Rj/JQneNny723QRNsAH7SGojf4ZAROMg ruDGe+rxOVz09mBypSOSF+dc6iVye6VReMLjmFiB0GSMwE+kLiJX+wryUF3F2eWa0rE+PvTNwmj mNQZgd1PeooTK/taF+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-03_03,2026-03-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603030196 On 3/3/2026 3:49 PM, Dmitry Baryshkov wrote: > On Tue, Mar 03, 2026 at 03:24:16PM -0800, Vijay Kumar Tumati wrote: >> >> >> On 3/3/2026 2:31 PM, Dmitry Baryshkov wrote: >>> On Mon, Mar 02, 2026 at 05:51:24PM -0800, Vijay Kumar Tumati wrote: >>>> Hi Bryan, >>>> >>>> On 2/26/2026 4:34 AM, Bryan O'Donoghue wrote: >>>>> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >>>> As we are cleaning up the PHY device nodes, we should consider fixing the >>>> power domains as well. Although TOP GDSC is defined as a power domain, it is >>>> not the power source for the PHY devices. Rather, it is the MMCX, MXC and >>>> optionally MXA based on the architecture (Refer to 'Voltage rail' column for >>>> PHY clocks in IPCAT). There is no >>>> parent-child relationship between the TOP GDSC and these in the clock driver >>>> and it was just working as the required power rails are getting enabled >>>> by/for other MM devices. >>> >>> Which domains are required to access CSI PHY registers? >> PHY register access requires the PHY core clock, cam_top_ahb clock. So in my >> understanding, we need to trace these clocks in the topology backwards up >> until at least the RCG, and all the voltage rails powering these clocks will >> be the required power domains. Having said that, just register access works >> even if the voltage rails are configured to the min level, which camcc does >> already. > > Are they not gated by the GDSC? All the Titan CAMCC clocks are gated by the TOP GDSC, yes. > >>> >>>>> + >>>>> + vdda-0p8-supply = <&vreg_l2c_0p8>; >>>>> + vdda-1p2-supply = <&vreg_l1c_1p2>; >>>>> + }; >>>>> + >>> >> Thanks, >> Vijay. > Thanks, Vijay.