From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D825F258EDA for ; Sun, 2 Aug 2026 16:15:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687359; cv=none; b=Wwf5li2j+oqQ65qFGqHATT3JpsU3K7i03kKsUTJK5b7tvVz5M95IhkJ4qfMLLWFctmyBBNWe5omDrF3xAvG4hDmTxuS9TEVhA9LDLcuzbgRoHh/xjbAK/aco3rV/FMmTd1WHUfyT9Y0OvpSfUulkan6ezSN4a6ZvLeBzpLXaVis= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785687359; c=relaxed/simple; bh=xK56fsihGvbjaA8O2I7hqGKbs9pu7T9JVte2XK4LDjA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TYB2xYL0jXcNh48GNqBCOkniUvZYqy/1t1+c08wq+/DfWMnFF7jnYB888d0LgGKQ1hIA4tphgTAXwbpfGUYN/z2GZREGHFunpYj64Y5usymNJ9NyGycrUchNleUg7kdM+4k9wE/5ERuwejylCxHImrHbapOutacZr4+DC4m8Ktg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MbmBOoCd; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MbmBOoCd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785687357; x=1817223357; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xK56fsihGvbjaA8O2I7hqGKbs9pu7T9JVte2XK4LDjA=; b=MbmBOoCdN3Bw1XuzNMsbcBNNtfDkITNbGo0/EnitkYGx50F5H7mJv5FK w/OlIzujcrcki+B51xwXNKUXzj6xPRVC9MqiBYXEThvfXqgx5mYRh3oxI XwG9ebW4D9Th+K0IrPH4hIsqgU89MEmpAorXj8fs+O0NN3xfi5HCWXXDM D0Bp7s/H07DcNndHTlxeX5ZW0WHE55HscR8hqtYVM98Q5mVWAc5MIgVu9 u8/wKXEH7SUO/sgeXmW9iqbZG1KJ4shoYo/Vvev3wmEOlk8Rv56IjCU0I 8t5uKcQI3/tj2Pg4g1DxKqzlQx/UsSCOc9jjoCJ2Nh5rEHt3dKiOZir5A Q==; X-CSE-ConnectionGUID: bgoSmF63RuCc0OaQO1NPBg== X-CSE-MsgGUID: I6ONKT6bSPejmVwSjIUr6g== X-IronPort-AV: E=McAfee;i="6800,10657,11863"; a="97612392" X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="97612392" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Aug 2026 09:15:56 -0700 X-CSE-ConnectionGUID: id9sEarCTReZO2Ku5UbuMQ== X-CSE-MsgGUID: KbaZEWvRSIesmArXNTIFdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,200,1779174000"; d="scan'208";a="261068774" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa007.jf.intel.com with ESMTP; 02 Aug 2026 09:15:53 -0700 From: Chen Yu To: Reinette Chatre , Tony Luck Cc: Ben Horgan , "James Morse" , Dave Martin , Babu Moger , Fenghua Yu , Borislav Petkov , Thomas Gleixner , "Dave Hansen" , Peter Newman , chen.yu@linux.dev, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 15/31] x86/resctrl: Parse ACPI MMRC table Date: Mon, 3 Aug 2026 00:06:11 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MMRC table is used to provide Memory Bandwidth Monitor Register information. Its register addresses are mapped, and the MMRC pointer is saved in the corresponding domain information entry. Signed-off-by: Chen Yu --- arch/x86/kernel/cpu/resctrl/erdt.c | 51 ++++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 6 ++- 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/erdt.c b/arch/x86/kernel/cpu/resctrl/erdt.c index 5f9377c80be6..a14de9eb8b88 100644 --- a/arch/x86/kernel/cpu/resctrl/erdt.c +++ b/arch/x86/kernel/cpu/resctrl/erdt.c @@ -24,6 +24,7 @@ static bool erdt_enabled; #define ERDT_VALID_VERSION 1 #define CMRC_SUPPORTED_INDEX_FN 1 +#define MMRC_SUPPORTED_INDEX_FN 1 #define RMDD_FLAG_CPU_L3_DOMAIN BIT(0) /* Set in a monitoring counter when it holds no valid data to report. */ @@ -141,6 +142,7 @@ static void cleanup_one_domain(struct erdt_domain_info *d) { erdt_iounmap_domain(d); kfree(d->cmrc); + kfree(d->mmrc); kfree(d); } @@ -211,6 +213,49 @@ static __init int cmrc_init(struct acpi_subtbl_hdr_16 *subtbl, return 0; } +static __init int mmrc_init(struct acpi_subtbl_hdr_16 *subtbl, + struct erdt_domain_info *domain_info) +{ + struct acpi_erdt_mmrc *mmrc = (struct acpi_erdt_mmrc *)subtbl; + + if (subtbl->length < sizeof(*mmrc)) { + pr_warn(FW_BUG "Truncated MMRC subtable\n"); + return -EIO; + } + + if (mmrc->index_fn != MMRC_SUPPORTED_INDEX_FN) { + pr_info("Unsupported MMRC index function %d\n", mmrc->index_fn); + return -EIO; + } + + /* + * The correction factor list is a trailing flexible array, so it is + * not covered by the sizeof(*mmrc) check above. Firmware could claim + * more entries than the sub-table actually carries, so only trust the + * length the sub-table can back. + */ + if (subtbl->length < struct_size(mmrc, corr_factor_list, + mmrc->corr_factor_list_len)) { + pr_warn(FW_BUG "MMRC correction factor list of %u entries exceeds sub-table\n", + mmrc->corr_factor_list_len); + return -EIO; + } + + domain_info->base[ERDT_MMIO_MMRC_BASE] = + erdt_ioremap(mmrc->reg_base, mmrc->reg_size, "MMRC base"); + if (!domain_info->base[ERDT_MMIO_MMRC_BASE]) + return -EIO; + + domain_info->mmrc = kmemdup(mmrc, subtbl->length, GFP_KERNEL); + if (!domain_info->mmrc) { + iounmap(domain_info->base[ERDT_MMIO_MMRC_BASE]); + domain_info->base[ERDT_MMIO_MMRC_BASE] = NULL; + return -ENOMEM; + } + + return 0; +} + static inline struct acpi_subtbl_hdr_16 *rmdd_subtbl(struct acpi_erdt_rmdd *rmdd) { return (void *)rmdd + sizeof(*rmdd); @@ -287,6 +332,12 @@ static __init bool parse_rmdd_table(struct acpi_subtbl_hdr_16 *rmdd_hdr) !cmrc_init(subtbl, domain_info)) subtbl_mask |= BIT(ACPI_ERDT_TYPE_CMRC); + break; + case ACPI_ERDT_TYPE_MMRC: + if (!(subtbl_mask & BIT(ACPI_ERDT_TYPE_MMRC)) && + !mmrc_init(subtbl, domain_info)) + subtbl_mask |= BIT(ACPI_ERDT_TYPE_MMRC); + break; default: break; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index c175d8884516..4bbe0c80c9e6 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -25,11 +25,13 @@ * Index into erdt_domain_info::base[] for each MMIO region. * @ERDT_MMIO_RMDD_CREG: RMDD control register base address * @ERDT_MMIO_CMRC_BASE: CMRC monitoring register base address + * @ERDT_MMIO_MMRC_BASE: MMRC monitoring register base address */ enum erdt_mmio_type { ERDT_MMIO_RMDD_CREG, ERDT_MMIO_CMRC_BASE, - ERDT_MMIO_LAST = ERDT_MMIO_CMRC_BASE + ERDT_MMIO_MMRC_BASE, + ERDT_MMIO_LAST = ERDT_MMIO_MMRC_BASE }; #define ERDT_MMIO_NUM_TYPES (ERDT_MMIO_LAST + 1) @@ -38,6 +40,7 @@ enum erdt_mmio_type { * struct erdt_domain_info - Per-domain ERDT information * @base: Array of ioremapped MMIO region base addresses, indexed by ERDT_MMIO_* type * @cmrc: Copy of the ACPI CMRC sub-table for this domain + * @mmrc: Copy of the ACPI MMRC sub-table for this domain * @cpu_mask: CPUs belonging to this resource management domain * @max_rmid: Maximum RMID supported by this domain * @dom_id: L3 cache ID shared by all CPUs in this domain (-1 if unset) @@ -46,6 +49,7 @@ enum erdt_mmio_type { struct erdt_domain_info { void __iomem *base[ERDT_MMIO_NUM_TYPES]; struct acpi_erdt_cmrc *cmrc; + struct acpi_erdt_mmrc *mmrc; struct cpumask cpu_mask; u32 max_rmid; int dom_id; -- 2.43.0