From: "Schaffner, Tobias" <tobias.schaffner@siemens.com>
To: "jszhang@kernel.org" <jszhang@kernel.org>
Cc: "anup@brainfault.org" <anup@brainfault.org>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"atishp@atishpatra.org" <atishp@atishpatra.org>,
"bigeasy@linutronix.de" <bigeasy@linutronix.de>,
"kvm-riscv@lists.infradead.org" <kvm-riscv@lists.infradead.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"palmer@dabbelt.com" <palmer@dabbelt.com>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"rostedt@goodmis.org" <rostedt@goodmis.org>,
"tglx@linutronix.de" <tglx@linutronix.de>
Subject: Re: [PATCH v2 0/5] riscv: add PREEMPT_RT support
Date: Tue, 14 Mar 2023 13:07:32 +0000 [thread overview]
Message-ID: <b615dd8b-27f3-702a-3c36-ab18df64d5aa@siemens.com> (raw)
In-Reply-To: <20220831175920.2806-1-jszhang@kernel.org>
On 31/08/2022 18:59, Jisheng Zhang wrote:
> This series is to add PREEMPT_RT support to riscv:
> patch1 adds the missing number of signal exits in vCPU stat
> patch2 switches to the generic guest entry infrastructure
> patch3 select HAVE_POSIX_CPU_TIMERS_TASK_WORK which is a requirement for
> RT
> patch4 adds lazy preempt support
> patch5 allows to enable PREEMPT_RT
>
> I assume patch1, patch2 and patch3 can be reviewed and merged for
> riscv-next, patch4 and patch5 can be reviewed and maintained in rt tree,
> and finally merged once the remaining patches in rt tree are all
> mainlined.
I tested the last two patches on a StarFive VisionFive V2 (DT) board
with 6.1.12-rt7-gdfa52cc14f3b today and the results looked pretty good
for a first run.
root@StarFive:~# lscpu
Architecture: riscv64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
root@StarFive:~# uname -a
Linux StarFive 6.1.12-rt7-gdfa52cc14f3b #1 SMP PREEMPT_RT Thu, 01 Jan
1970 01:00:00 +0000 riscv64 GNU/Linuxb
root@StarFive:~# cat /proc/cmdline
initrd=\initrd.img-6.1.12-rt7-gdfa52cc14f3b LABEL=Boot
root=PARTUUID=7176479f-eeea-46ac-afb6-7ec47ff7c390 console=tty0
console=ttyS0,115200 earlycon rootwait isolcpus=2-3 rcu_nocbs=2-3
nohz_full=2-3 irqaffinity=0-1
root@StarFive:~# cyclictest -m -S -p 90 -i 50 -d 0 -q -D 10m
WARN: stat /dev/cpu_dma_latency failed: No such file or directory
T: 0 ( 358) P:90 I:50 C:11999999 Min: 11 Act: 11 Avg: 11 Max:
55
T: 1 ( 359) P:90 I:50 C:11999241 Min: 11 Act: 11 Avg: 11 Max:
60
Feel free to reach out for further tests or logs.
Best,
Tobias
> Since v1:
> - send to related maillist, I press ENTER too quickly when sending v1
> - remove the signal_pending() handling because that's covered by
> generic guest entry infrastructure
>
> Jisheng Zhang (5):
> RISC-V: KVM: Record number of signal exits as a vCPU stat
> RISC-V: KVM: Use generic guest entry infrastructure
> riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK
> riscv: add lazy preempt support
> riscv: Allow to enable RT
>
> arch/riscv/Kconfig | 3 +++
> arch/riscv/include/asm/kvm_host.h | 1 +
> arch/riscv/include/asm/thread_info.h | 7 +++++--
> arch/riscv/kernel/asm-offsets.c | 1 +
> arch/riscv/kernel/entry.S | 9 +++++++--
> arch/riscv/kvm/Kconfig | 1 +
> arch/riscv/kvm/vcpu.c | 18 +++++++-----------
> 7 files changed, 25 insertions(+), 15 deletions(-)
>
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
prev parent reply other threads:[~2023-03-14 13:11 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-31 17:59 Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 1/5] RISC-V: KVM: Record number of signal exits as a vCPU stat Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 2/5] RISC-V: KVM: Use generic guest entry infrastructure Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 3/5] riscv: select HAVE_POSIX_CPU_TIMERS_TASK_WORK Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 4/5] riscv: add lazy preempt support Jisheng Zhang
2022-09-04 15:16 ` Guo Ren
2022-09-05 6:34 ` Sebastian Andrzej Siewior
2022-09-05 8:33 ` Guo Ren
2022-09-05 8:46 ` Sebastian Andrzej Siewior
2022-09-06 1:46 ` Guo Ren
2022-09-05 12:58 ` Jisheng Zhang
2022-08-31 17:59 ` [PATCH v2 5/5] riscv: Allow to enable RT Jisheng Zhang
2022-09-01 7:04 ` [PATCH v2 0/5] riscv: add PREEMPT_RT support Sebastian Andrzej Siewior
2022-09-01 13:44 ` Jisheng Zhang
2022-09-01 16:41 ` Conor.Dooley
2022-09-02 13:09 ` Jisheng Zhang
2022-09-02 13:29 ` Conor.Dooley
2022-11-11 14:32 ` Sebastian Andrzej Siewior
2022-11-11 14:34 ` Conor.Dooley
2022-11-12 21:40 ` Conor.Dooley
2023-03-14 13:07 ` Schaffner, Tobias [this message]
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