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Thu, 26 Jan 2023 06:26:24 -0600 Received: from [10.250.234.92] (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30QCQKcU012290; Thu, 26 Jan 2023 06:26:21 -0600 Message-ID: Date: Thu, 26 Jan 2023 17:56:19 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v8 3/8] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI Content-Language: en-US To: Ravi Gunasekaran , , , , , , CC: , , References: <20230123095733.31657-1-r-gunasekaran@ti.com> <20230123095733.31657-4-r-gunasekaran@ti.com> From: Vignesh Raghavendra In-Reply-To: <20230123095733.31657-4-r-gunasekaran@ti.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/01/23 3:27 pm, Ravi Gunasekaran wrote: > From: Aswath Govindraju > > Add support for two instance of OSPI in J721S2 SoC. > > Signed-off-by: Aswath Govindraju > Signed-off-by: Matt Ranostay > Reviewed-by: Vaishnav Achath > Link: https://lore.kernel.org/r/20221122101616.770050-4-mranostay@ti.com > Signed-off-by: Ravi Gunasekaran > --- > .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 39 +++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > index 0af242aa9816..d404b595316e 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi > @@ -306,4 +306,43 @@ > ti,cpts-periodic-outputs = <2>; > }; > }; > + > + fss: bus@47000000 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + make dtbs W=12 Warning (unit_address_vs_reg): /bus@100000/bus@28380000/bus@47000000: node has a unit name, but no reg or ranges property > + ospi0: spi@47040000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47040000 0x00 0x100>, > + <0x5 0x0000000 0x1 0x0000000>; Also, please follow existing convention <0x05 0x00000000 0x01 0x0000000>; > + interrupts = ; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 109 5>; > + assigned-clocks = <&k3_clks 109 5>; > + assigned-clock-parents = <&k3_clks 109 7>; > + assigned-clock-rates = <166666666>; > + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + ospi1: spi@47050000 { > + compatible = "ti,am654-ospi", "cdns,qspi-nor"; > + reg = <0x00 0x47050000 0x00 0x100>, > + <0x7 0x0000000 0x1 0x0000000>; <0x07 0x00000000 0x01 0x0000000>; > + interrupts = ; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 110 5>; > + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + }; > };