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Wed, 25 Jun 2025 10:38:30 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 55PAcTpT029099 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Jun 2025 10:38:29 GMT Received: from [10.217.217.109] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 25 Jun 2025 03:38:24 -0700 Message-ID: Date: Wed, 25 Jun 2025 16:08:21 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 07/10] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Will Deacon , Catalin Marinas CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , , Dmitry Baryshkov References: <20250612-qcs615-mm-v9-clock-controllers-v9-0-b34dc78d6e1b@quicinc.com> <20250612-qcs615-mm-v9-clock-controllers-v9-7-b34dc78d6e1b@quicinc.com> <75fea0f5-88ca-4099-ba48-997e46bf4de5@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: <75fea0f5-88ca-4099-ba48-997e46bf4de5@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: j_y1SPe-6nBJhxdf0dbmSXZUwvqCZytd X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI1MDA3OSBTYWx0ZWRfXx8+CG4SjSGyo k1TdYB3Am8HL2UmZ4Asb6sf9O+mD4eWdXy574VxzioW6pKrG0hORWAdoScxjgc5YtXE4iZsR1Y9 p4A6YbDfqi9NTaX7GRLuF/hAA5uqjfJE22dfhaMTClm1eM2yX8JyP2jOoINMS/OhEUzpEKpea/g 38hYSaeEpPnYgi7G7eIyZu18FEBXhhIDg+mcR1SI47081Ej2udjgJRalLcgET/aGDY5+1cJuZSP CDVmTB7UC1GkE9qABywEtadzcdDhX7VMHEDfgZ1N1YoR6SJ2lplBJ99qGJ78KVCjL8+L0ukizS+ QwnTRHJ/bzZYpi1515VdSlcP37DeurCzI4p+AKv1f++gFUvElna9zc/zddm7TQINJ8G3oCnJqpi BcSyjZnehin4qYSr32WR/z3MCGmXcul1EFu5YyHbIAdlbTxFXQtIbnoiIV9Jaoj8iTH8HY3L X-Authority-Analysis: v=2.4 cv=L4kdQ/T8 c=1 sm=1 tr=0 ts=685bd1a6 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=6G9fbBdXaqdFCPydoIcA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: j_y1SPe-6nBJhxdf0dbmSXZUwvqCZytd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-25_02,2025-06-23_07,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506250079 On 6/15/2025 12:49 AM, Konrad Dybcio wrote: > On 6/12/25 11:55 AM, Taniya Das wrote: >> Add support for the graphics clock controller for graphics clients to >> be able to request for the clocks on QCS615 platform. >> >> Reviewed-by: Dmitry Baryshkov >> Signed-off-by: Taniya Das >> --- > > [...] > >> +struct clk_hw *gpu_cc_sm6150_hws[] = { > > "wink" > My bad. > [...] > >> +static void configure_crc(struct regmap *regmap) >> +{ >> + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ >> + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, 0xff0, 0xff0); >> + >> + /* >> + * After POR, Clock Ramp Controller(CRC) will be in bypass mode. >> + * Software needs to do the following operation to enable the CRC >> + * for GFX3D clock and divide the input clock by div by 2. >> + */ >> + regmap_update_bits(regmap, 0x1028, 0x00015011, 0x00015011); >> + regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000); > > I'm going to assume this is not the same ramp controller as: > > drivers/soc/qcom/ramp_controller.c > This ramp controller is at the RCG level, which was very specific to 8976 and not same at the CC level. > ..or maybe it is one, but we need to set things up on the CC > side > >> +} >> + >> +static int gpu_cc_qcs615_probe(struct platform_device *pdev) >> +{ >> + struct regmap *regmap; >> + >> + regmap = qcom_cc_map(pdev, &gpu_cc_qcs615_desc); >> + if (IS_ERR(regmap)) >> + return PTR_ERR(regmap); >> + >> + clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); >> + clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); >> + >> + /* Keep some clocks always enabled */ >> + qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ >> + >> + configure_crc(regmap); > > Likewise, please rebase on Jagadeesh's series, which is now in > linux-next. With that: > I will fix them in the next patch series. > Reviewed-by: Konrad Dybcio > > Konrad