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X-CSE-ConnectionGUID: dWf3jn5NQ8iS90BHOAB0Mw== X-CSE-MsgGUID: rDeur7/fQWS1vig0PrgX2A== X-IronPort-AV: E=McAfee;i="6800,10657,11631"; a="66904574" X-IronPort-AV: E=Sophos;i="6.20,248,1758610800"; d="scan'208";a="66904574" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 04:11:29 -0800 X-CSE-ConnectionGUID: RiQOp9yrQUOAIi9w0Fy0lA== X-CSE-MsgGUID: E3ame0wpQHeZvwt3CoAvRA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,248,1758610800"; d="scan'208";a="194789577" Received: from mjarzebo-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.11]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Dec 2025 04:11:24 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v7 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing In-Reply-To: <20251202110218.9212-6-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251202110218.9212-1-iam@lach.pw> <20251202110218.9212-6-iam@lach.pw> Date: Thu, 04 Dec 2025 14:11:20 +0200 Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Tue, 02 Dec 2025, Yaroslav Bolyukin wrote: > Other usages of block.rev bitfields were refactored to use FIELD_GET > instead of bitwise ops. > > Signed-off-by: Yaroslav Bolyukin Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_displayid_internal.h | 1 + > drivers/gpu/drm/drm_edid.c | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h > index 724174b429f2..55f972d32847 100644 > --- a/drivers/gpu/drm/drm_displayid_internal.h > +++ b/drivers/gpu/drm/drm_displayid_internal.h > @@ -139,6 +139,7 @@ struct displayid_formula_timings_9 { > u8 vrefresh; > } __packed; > > +#define DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES GENMASK(6, 4) > struct displayid_formula_timing_block { > struct displayid_block base; > struct displayid_formula_timings_9 timings[]; > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index b28ff4bafb1d..be8715632b91 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6908,7 +6908,8 @@ static int add_displayid_formula_modes(struct drm_connector *connector, > struct drm_display_mode *newmode; > int num_modes = 0; > bool type_10 = block->tag == DATA_BLOCK_2_TYPE_10_FORMULA_TIMING; > - int timing_size = 6 + ((formula_block->base.rev & 0x70) >> 4); > + int timing_size = 6 + > + FIELD_GET(DISPLAYID_BLOCK_DESCRIPTOR_PAYLOAD_BYTES, formula_block->base.rev); > > /* extended blocks are not supported yet */ > if (timing_size != 6) -- Jani Nikula, Intel