From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Rob Clark" <robdclark@gmail.com>,
quic_abhinavk@quicinc.com, "Sean Paul" <sean@poorly.run>,
"Marijn Suijten" <marijn.suijten@somainline.org>,
"David Airlie" <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
quic_ebharadw@quicinc.com, linux-arm-msm@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org,
"Rob Clark" <robdclark@chromium.org>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v2 06/22] drm/msm/dpu: fill CRTC resources in dpu_crtc.c
Date: Tue, 24 Sep 2024 17:37:30 -0700 [thread overview]
Message-ID: <b66264a9-2ff9-482a-96e0-453d55bc651c@quicinc.com> (raw)
In-Reply-To: <4c7spborzltmvjlbd2o4uwknraitjtf34mqt7r3x2ospnaidyn@abvn5zdumvwt>
On 9/24/2024 4:16 PM, Dmitry Baryshkov wrote:
> On Tue, Sep 24, 2024 at 03:59:22PM GMT, Jessica Zhang wrote:
>> From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>
>> Stop poking into CRTC state from dpu_encoder.c, fill CRTC HW resources
>> from dpu_crtc_assign_resources().
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> [quic_abhinavk@quicinc.com: cleaned up formatting]
>> Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
>> [quic_jesszhan@quicinc.com: dropped clearing num_mixers in CRTC disable
>> path]
>
> Same comment as before: the code is still there.
Hi Dmitry,
I thought the original comment was to move the dropping `num_mixers = 0`
chunk from the previous patch to this one?
Sorry if I misunderstood.
Thanks,
Jessica Zhang
>
>> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 32 ++++++++++++++++++++++++++---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 24 ++--------------------
>> 2 files changed, 31 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> index b918c80d30b3..d53e986eee54 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
>> @@ -1091,9 +1091,6 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
>>
>> dpu_core_perf_crtc_update(crtc, 0);
>>
>> - memset(cstate->mixers, 0, sizeof(cstate->mixers));
>> - cstate->num_mixers = 0;
>> -
>> /* disable clk & bw control until clk & bw properties are set */
>> cstate->bw_control = false;
>> cstate->bw_split_vote = false;
>> @@ -1164,6 +1161,7 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
>> }
>>
>> #define MAX_HDISPLAY_SPLIT 1080
>> +#define MAX_CHANNELS_PER_CRTC 2
>>
>> static struct msm_display_topology dpu_crtc_get_topology(
>> struct drm_crtc *crtc,
>> @@ -1208,9 +1206,14 @@ static struct msm_display_topology dpu_crtc_get_topology(
>>
>> static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
>> {
>> + struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC];
>> + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC];
>> + struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC];
>> + int i, num_lm, num_ctl, num_dspp;
>> struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
>> struct dpu_global_state *global_state;
>> struct msm_display_topology topology;
>> + struct dpu_crtc_state *cstate;
>> int ret;
>>
>> /*
>> @@ -1232,6 +1235,29 @@ static int dpu_crtc_assign_resources(struct drm_crtc *crtc, struct drm_crtc_stat
>> if (ret)
>> return ret;
>>
>> + cstate = to_dpu_crtc_state(crtc_state);
>> +
>> + num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> + crtc, DPU_HW_BLK_CTL, hw_ctl,
>> + ARRAY_SIZE(hw_ctl));
>> + num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> + crtc, DPU_HW_BLK_LM, hw_lm,
>> + ARRAY_SIZE(hw_lm));
>> + num_dspp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> + crtc, DPU_HW_BLK_DSPP, hw_dspp,
>> + ARRAY_SIZE(hw_dspp));
>> +
>> + for (i = 0; i < num_lm; i++) {
>> + int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
>> +
>> + cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
>> + cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
>> + if (i < num_dspp)
>> + cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
>> + }
>> +
>> + cstate->num_mixers = num_lm;
>> +
>> return 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> index ada9119326ca..36b677cf9c7a 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
>> @@ -1049,14 +1049,11 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
>> struct dpu_encoder_virt *dpu_enc;
>> struct msm_drm_private *priv;
>> struct dpu_kms *dpu_kms;
>> - struct dpu_crtc_state *cstate;
>> struct dpu_global_state *global_state;
>> struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
>> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
>> - struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
>> - struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
>> struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
>> - int num_lm, num_ctl, num_pp, num_dsc;
>> + int num_pp, num_dsc;
>> unsigned int dsc_mask = 0;
>> int i;
>>
>> @@ -1083,13 +1080,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
>> num_pp = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> drm_enc->crtc, DPU_HW_BLK_PINGPONG, hw_pp,
>> ARRAY_SIZE(hw_pp));
>> - num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> - drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
>> - num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> - drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
>> dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
>> - drm_enc->crtc, DPU_HW_BLK_DSPP, hw_dspp,
>> - ARRAY_SIZE(hw_dspp));
>> + drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl));
>
> Please don't mix reindentation with the actual changes. It makes it
> harder to read.
>
>>
>> for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
>> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
>> @@ -1115,18 +1107,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
>> dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
>> }
>>
>> - cstate = to_dpu_crtc_state(crtc_state);
>> -
>> - for (i = 0; i < num_lm; i++) {
>> - int ctl_idx = (i < num_ctl) ? i : (num_ctl-1);
>> -
>> - cstate->mixers[i].hw_lm = to_dpu_hw_mixer(hw_lm[i]);
>> - cstate->mixers[i].lm_ctl = to_dpu_hw_ctl(hw_ctl[ctl_idx]);
>> - cstate->mixers[i].hw_dspp = to_dpu_hw_dspp(hw_dspp[i]);
>> - }
>> -
>> - cstate->num_mixers = num_lm;
>> -
>> for (i = 0; i < dpu_enc->num_phys_encs; i++) {
>> struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
>>
>>
>> --
>> 2.34.1
>>
>
> --
> With best wishes
> Dmitry
next prev parent reply other threads:[~2024-09-25 0:37 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 22:59 [PATCH v2 00/22] drm/msm/dpu: Add Concurrent Writeback Support for DPU 10.x+ Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 01/22] drm: add clone mode check for CRTC Jessica Zhang
2024-09-24 23:06 ` Dmitry Baryshkov
2024-09-25 7:22 ` Maxime Ripard
2024-09-25 8:12 ` Jani Nikula
2024-09-25 20:47 ` Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 02/22] drm: Add valid clones check Jessica Zhang
2024-09-25 7:23 ` Maxime Ripard
2024-12-07 0:48 ` Jessica Zhang
2024-12-16 2:19 ` Abhinav Kumar
2024-12-16 14:27 ` Simona Vetter
2024-12-16 19:44 ` Jessica Zhang
2024-12-16 14:47 ` Maxime Ripard
2024-12-16 19:47 ` Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 03/22] drm/msm/dpu: get rid of struct dpu_rm_requirements Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 04/22] drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 05/22] drm/msm/dpu: move resource allocation to CRTC Jessica Zhang
2024-09-24 23:13 ` Dmitry Baryshkov
2024-09-25 20:38 ` Jessica Zhang
2024-09-25 21:11 ` Dmitry Baryshkov
2024-09-25 21:49 ` Abhinav Kumar
2024-09-26 7:12 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 06/22] drm/msm/dpu: fill CRTC resources in dpu_crtc.c Jessica Zhang
2024-09-24 23:16 ` Dmitry Baryshkov
2024-09-25 0:37 ` Jessica Zhang [this message]
2024-09-25 8:17 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 07/22] drm/msm/dpu: Add CWB entry to catalog for SM8650 Jessica Zhang
2024-09-24 23:17 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 08/22] drm/msm/dpu: Specify dedicated CWB pingpong blocks Jessica Zhang
2024-09-24 23:17 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 09/22] drm/msm/dpu: add devcoredumps for cwb registers Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 10/22] drm/msm/dpu: Add dpu_hw_cwb abstraction for CWB block Jessica Zhang
2024-09-24 23:19 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 11/22] drm/msm/dpu: add CWB support to dpu_hw_wb Jessica Zhang
2024-09-24 23:20 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 12/22] drm/msm/dpu: Add RM support for allocating CWB Jessica Zhang
2024-09-24 23:20 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 13/22] drm/msm/dpu: Add CWB to msm_display_topology Jessica Zhang
2024-09-24 23:22 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 14/22] drm/msm/dpu: Require modeset if clone mode status changes Jessica Zhang
2024-09-24 23:25 ` Dmitry Baryshkov
2024-09-25 0:05 ` Abhinav Kumar
2024-09-25 8:28 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 15/22] drm/msm/dpu: Reserve resources for CWB Jessica Zhang
2024-09-24 23:33 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 16/22] drm/msm/dpu: Configure CWB in writeback encoder Jessica Zhang
2024-09-24 23:41 ` Dmitry Baryshkov
2024-09-25 0:14 ` Jessica Zhang
2024-09-25 8:30 ` Dmitry Baryshkov
2024-09-30 14:17 ` neil.armstrong
2024-09-30 19:19 ` Jessica Zhang
2024-10-01 7:37 ` neil.armstrong
2024-10-08 8:00 ` Neil Armstrong
2024-10-08 8:18 ` Maxime Ripard
2024-10-08 12:25 ` Jessica Zhang
2024-10-09 7:46 ` neil.armstrong
2024-09-24 22:59 ` [PATCH v2 17/22] drm/msm/dpu: Support CWB in dpu_hw_ctl Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 18/22] drm/msm/dpu: Adjust writeback phys encoder setup for CWB Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 19/22] drm/msm/dpu: Start frame done timer after encoder kickoff Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 20/22] drm/msm/dpu: Skip trigger flush and start for CWB Jessica Zhang
2024-09-24 23:43 ` Dmitry Baryshkov
2024-09-24 22:59 ` [PATCH v2 21/22] drm/msm/dpu: Reorder encoder kickoff " Jessica Zhang
2024-09-24 22:59 ` [PATCH v2 22/22] drm/msm/dpu: Set possible clones for all encoders Jessica Zhang
2024-09-24 23:44 ` Dmitry Baryshkov
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