From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3119230CD8B for ; Tue, 9 Dec 2025 21:39:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765316376; cv=none; b=DMoSrbxI0HxZ5r/LfUDPkAdEkRKXJR87TqY9PmqMaybnanjY6RKPsukW9D2hhQozPRttX42SMhnxLzl/WW8HbzqLMQIQxHqjEubQf50MmoqjIwLdpQhSrCpsa6o+BsqTr4iOo7mRvcWKTjThhgK8dIsWeoOFfNKELInCKr+HfcQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765316376; c=relaxed/simple; bh=10Zcnk7hG5DBcbNw8cgqzriIdC8InpDR/2H4xih+/CU=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=FtI7CzlYH4e28YdjC4MQp+Yljw1O7r77GImeuRignJDrg/D5AzmGGuiSy5Bq92LY299Mxuhslad3Yv+CkEUS/Priq7tHMqVcNhMlHCJhNyEUZcsH5GGyyyKl9Rh1iAehzOb0vsrETIZ9tbk0A9BkXkogzLX/1WG/HE+W/a4+xaQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ViNpSnZ3; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ViNpSnZ3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1765316374; x=1796852374; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=10Zcnk7hG5DBcbNw8cgqzriIdC8InpDR/2H4xih+/CU=; b=ViNpSnZ3+uk+e/eMi/hq9k4IyNgUO4DUyMzUcbunzF7oQktHpSKg6FPW GKI4BqZoUSp93l7eWTtA4aUb1MELSbXqHoZ7ktBlBW3GsKbUdLtC25mF1 fOSIMd1Uvt0dvKFvyJsxo3z6LpCCtfUpqjggOBTPxwBNLHRcJIugdML0U GVAfr4IhrVyAk7/tTP2ds89sn2nkSpthHKMh79ktbxPLazPbEQz5A4MwP AFSvVxWhLWP4r0Pa8GaWNQiQ8ozeIuYzuAy4gRBfB2VX6nu+K5BZTgzgw 4nar3bCwRtb4NjTfLOHR8YpMW+HSd5ZjTboUZgTHDaKekXgmebBcN8F2q w==; X-CSE-ConnectionGUID: 1rHBe8IcSAmTcQYoa+2FzQ== X-CSE-MsgGUID: wPVkxyIXTYu+8Nw76SOdjA== X-IronPort-AV: E=McAfee;i="6800,10657,11637"; a="67008329" X-IronPort-AV: E=Sophos;i="6.20,262,1758610800"; d="scan'208";a="67008329" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2025 13:39:33 -0800 X-CSE-ConnectionGUID: hH5Reh0EQdOJ/21cdNX1zQ== X-CSE-MsgGUID: i4KhD7HZTC+WEHRy0gRkkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,262,1758610800"; d="scan'208";a="233740392" Received: from unknown (HELO [10.241.243.18]) ([10.241.243.18]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Dec 2025 13:39:33 -0800 Message-ID: Subject: Re: [PATCH v2 01/23] sched/cache: Introduce infrastructure for cache-aware load balancing From: Tim Chen To: Peter Zijlstra Cc: Ingo Molnar , K Prateek Nayak , "Gautham R . Shenoy" , Vincent Guittot , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Aubrey Li , Zhao Liu , Chen Yu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , linux-kernel@vger.kernel.org Date: Tue, 09 Dec 2025 13:39:32 -0800 In-Reply-To: <20251209111244.GJ3707891@noisy.programming.kicks-ass.net> References: <06f0d7edbc3185ec730b50b3b00d87ace44169b3.1764801860.git.tim.c.chen@linux.intel.com> <20251209111244.GJ3707891@noisy.programming.kicks-ass.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.1 (3.58.1-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2025-12-09 at 12:12 +0100, Peter Zijlstra wrote: > On Wed, Dec 03, 2025 at 03:07:20PM -0800, Tim Chen wrote: >=20 > > Minor fix in task_tick_cache() to use > > if (mm->mm_sched_epoch >=3D rq->cpu_epoch) > > to avoid mm_sched_epoch going backwards. >=20 > > +static void task_tick_cache(struct rq *rq, struct task_struct *p) > > +{ > > + struct callback_head *work =3D &p->cache_work; > > + struct mm_struct *mm =3D p->mm; > > + > > + if (!sched_cache_enabled()) > > + return; > > + > > + if (!mm || !mm->pcpu_sched) > > + return; > > + > > + /* avoid moving backwards */ > > + if (mm->mm_sched_epoch >=3D rq->cpu_epoch) > > + return; >=20 > IIRC this was supposed to be able to wrap; which then means you should > write it like: >=20 > if ((mm->mm_sched_epoch - rq->cpu_epoch) >=3D 0) > return; >=20 > or somesuch. Okay. Got it. Tim >=20 > > + > > + guard(raw_spinlock)(&mm->mm_sched_lock); > > + > > + if (work->next =3D=3D work) { > > + task_work_add(p, work, TWA_RESUME); > > + WRITE_ONCE(mm->mm_sched_epoch, rq->cpu_epoch); > > + } > > +}