Re: [PATCH v3 3/8] x86/apic: Add an SVSM APIC driver

[Melody Wang <huibo.wang@amd.com>]

Hi all,

On 9/20/26 11:16 AM, Melody Wang wrote:
> +
> +static u32 __svsm_apic_msr_rw(u32 reg, u32 v, bool write)
> +{
> +	u32 msr = APIC_BASE_MSR + (reg >> 4);
> +	struct svsm_call call = {};
> +	const char *call_reg_str;
> +	unsigned int call_reg;
> +	int ret;
> +
> +	call_reg = write ? SVSM_APIC_WRITE_REGISTER
> +			 : SVSM_APIC_READ_REGISTER;
> +
> +	call_reg_str = write ? "SVSM_APIC_WRITE_REGISTER"
> +			     : "SVSM_APIC_READ_REGISTER";
> +
> +	switch (reg) {
> +	case APIC_ID:
> +	case APIC_TASKPRI:
> +	case APIC_PROCPRI:
> +	case APIC_EOI:
> +	case APIC_ISR ... APIC_ISR + 0x70:
> +	case APIC_TMR ... APIC_TMR + 0x70:
> +	case APIC_IRR ... APIC_IRR + 0x70:
> +	case APIC_ICR:
> +	case APIC_SELF_IPI:
> +		call.rax = SVSM_APIC_CALL(call_reg);
> +		call.rcx = msr;
> +		call.rdx = v;
> +
> +		ret = svsm_perform_call_protocol(&call);

Sashiko said this:

"Can this SVSM APIC call be interrupted by an NMI, causing CAA page
corruption and guest termination?
If a normal thread or IRQ handler executes an SVSM APIC operation and an
NMI fires exactly between setting call_pending to 1 and the vmmcall
instruction inside svsm_issue_call(), the NMI handler might execute another
APIC operation.
The nested SVSM call from the NMI would use the exact same per-CPU Calling
Area Address (CAA) page, clearing call_pending to 0. When the interrupted
call resumes, svsm_process_result_codes() would misinterpret the unmodified
input registers as an error code because call_pending is 0.
Does this result in ret being non-zero and triggering sev_es_terminate()
fatally crashing the guest?"


This will happen when there is APIC operation happening in the NMI 
handler, there is no such case so I would keep the code as it is for now 
unless there is some use case that needs us to do an APIC operation in 
the NMI handler in the future.

Thanks,
Melody