From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39D3F22DF9E for ; Mon, 15 Sep 2025 10:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757931478; cv=none; b=gohS8M1dJZgPplKSYfUTkS4NirSVA1vYRbW9hP+e7Oyw3B5hFRe3KAH12I/C78oNezn1wgTfQJXxELDQnEklFzJh4/juPFNhmiq55g4bWOdzGiZWqQ1kaKQHGJuIZzNuDbndyJlJY4/N4xI1A/9tdSFbsYNMhowF8yfAjTe1yc0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757931478; c=relaxed/simple; bh=CkiX+SfKyNNzh/CR0iQ6mQNKdawIAKfXA08rWVJaslk=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=r3S0Vl1Uaf+zDP0JqM4RgVJkGUdDCAdBEOM6LAC4mGncSAbBBL4j1zzqcxkAQihyEm42d8y3HOWsUI7eK0E9WznO6vM6YnWAwdK5kDqHMmawMW76hJzzjRb7Rmul3InRhObI2X4oEKUuIlz8HNPpCMa0YGs6aD56AHwEs+FPkbA= ARC-Authentication-Results:i=1; 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charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, On 15/09/2025 11:55, Swamil Jain wrote: > Hi, > > On 9/15/25 13:27, Maxime Ripard wrote: >> On Thu, Sep 11, 2025 at 04:37:15PM +0530, Swamil Jain wrote: >>> From: Jayesh Choudhary >>> >>> Since OLDI consumes DSS VP clock directly as serial clock, mode_valid() >>> check cannot be performed in tidss driver which should be checked >>> in OLDI driver. >>> >>> Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") >>> Tested-by: Michael Walle >>> Reviewed-by: Devarsh Thakkar >>> Signed-off-by: Jayesh Choudhary >>> Signed-off-by: Swamil Jain >>> --- >>>   drivers/gpu/drm/tidss/tidss_oldi.c | 21 +++++++++++++++++++++ >>>   1 file changed, 21 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/tidss/tidss_oldi.c b/drivers/gpu/drm/ >>> tidss/tidss_oldi.c >>> index 7ecbb2c3d0a2..ada691839ef3 100644 >>> --- a/drivers/gpu/drm/tidss/tidss_oldi.c >>> +++ b/drivers/gpu/drm/tidss/tidss_oldi.c >>> @@ -309,6 +309,26 @@ static u32 >>> *tidss_oldi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, >>>       return input_fmts; >>>   } >>>   +static int tidss_oldi_atomic_check(struct drm_bridge *bridge, >>> +                   struct drm_bridge_state *bridge_state, >>> +                   struct drm_crtc_state *crtc_state, >>> +                   struct drm_connector_state *conn_state) >>> +{ >>> +    struct tidss_oldi *oldi = drm_bridge_to_tidss_oldi(bridge); >>> +    struct drm_display_mode *adjusted_mode; >>> +    unsigned long round_clock; >>> + >>> +    adjusted_mode = &crtc_state->adjusted_mode; >>> +    round_clock = clk_round_rate(oldi->serial, adjusted_mode->clock >>> * 7 * 1000); >>> +    /* >>> +     * To keep the check consistent with dispc_vp_set_clk_rate(), >>> +     * we use the same 5% check here. >>> +     */ >>> +    if (dispc_pclk_diff(adjusted_mode->clock * 7 * 1000, >>> round_clock) > 5) >>> +        return -EINVAL; >>> +    return 0; >>> +} >>> + >> >> If you're introducing that check to tidss, please use .5% like everyone >> else. I understand that you don't want to change tilcdc to avoid any >> regression, but that's not the case here >> > This is just to make the tolerance check consistent for mode validation > and setting clock rate. This patch isn't introducing anything new, we > are following this as dispc_vp_set_clk_rate() and > tidss_oldi_set_serial_clk() are already checking for 5% tolerance while > setting clock. To remove/modify, this needs extensive testing with other > K3 and K2G SoCs and can be handled as a separate patch. I'd like to switch to 0.5%, but as Swamil said, I think it's better to do it on top. Tomi