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Wed, 04 Feb 2026 09:45:53 -0800 (PST) X-Received: by 2002:a05:6a21:150d:b0:393:39a0:f1df with SMTP id adf61e73a8af0-393725d732emr3402838637.78.1770227153461; Wed, 04 Feb 2026 09:45:53 -0800 (PST) Received: from [192.168.0.103] ([124.123.178.21]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c6d9713cb83sm219304a12.5.2026.02.04.09.45.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Feb 2026 09:45:53 -0800 (PST) Message-ID: Date: Wed, 4 Feb 2026 23:14:56 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/8] dt-bindings: clock: qcom: Add X1P42100 video clock controller To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260128-purwa-videocc-camcc-v1-0-b23de57df5ba@oss.qualcomm.com> <20260128-purwa-videocc-camcc-v1-1-b23de57df5ba@oss.qualcomm.com> Content-Language: en-US From: Jagadeesh Kona In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjA0MDEzNSBTYWx0ZWRfX5LAdNzbZWnsY wl/K/pOMfNUmshOsyKUp5iH/zvxckTUg1qETA5mETkC5wSgcss/zaL3g/yTDVwWoouQtKZLVstL zgEIBK6qBRxJ3zCLeTk/1NRG6JA/tBwXKXumyL+IZd+tYAelf9J+BDeaQZQrF1dPz115SZryA3O 81luJj9CPxkEndhq7wPEIq8OAlnGIZc3DLjrE9WzFSHPBzMq83pdCY2hkDZ03YPGhNvgO9e8WPc nAqVJF/Y9dUzRPeYtJNbzCMDfDvWEls0PnXKChHHWstBD2dn5ae+G40RbL7o7ixAQhvs8s2pG7H bz75YfcJqQfPoU+aU6OocKof0BLbHCpjmHWDPI364n+Vq4W/8F88IrCasVcjNBCPVqORlizaQ8l UgyW28VKbh3I2xy5ao0kdGdlRaSZfP8omeNoWhgk+I21FaeEtJgaExi5lXUxVGoriYveGJhL662 jBg/duAvnukYSvgAx2g== X-Proofpoint-ORIG-GUID: GEY_mRI0H5zdkzntNISZCU-T-jarxRvL X-Authority-Analysis: v=2.4 cv=GvhPO01C c=1 sm=1 tr=0 ts=698385d3 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=2H5/5ZkxJs/wMzWGxXwROQ==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=6d1n1Ba-E67CpG4V2ygA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: GEY_mRI0H5zdkzntNISZCU-T-jarxRvL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-04_06,2026-02-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 impostorscore=0 clxscore=1015 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602040135 On 1/28/2026 2:04 AM, Dmitry Baryshkov wrote: > On Wed, Jan 28, 2026 at 12:56:32AM +0530, Jagadeesh Kona wrote: >> X1P42100 video clock controller has most clocks same as SM8650, >> but it also has few additional clocks and resets. Add device >> tree bindings for the video clock controller on Qualcomm >> X1P42100 platform by defining these additional clocks and resets >> on top of SM8650. >> >> Signed-off-by: Jagadeesh Kona >> --- >> .../bindings/clock/qcom,sm8450-videocc.yaml | 2 ++ >> include/dt-bindings/clock/qcom,x1p42100-videocc.h | 21 +++++++++++++++++++++ >> 2 files changed, 23 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> index e6beebd6a36ee1ce213a816f60df8a76fa5c44d6..e8bf3fcad3fabc4f3b7e8e692c6c634d1aed9605 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml >> @@ -30,6 +30,7 @@ properties: >> - qcom,sm8650-videocc >> - qcom,sm8750-videocc >> - qcom,x1e80100-videocc >> + - qcom,x1p42100-videocc >> >> clocks: >> items: >> @@ -67,6 +68,7 @@ allOf: >> - qcom,sm8450-videocc >> - qcom,sm8550-videocc >> - qcom,sm8750-videocc >> + - qcom,x1p42100-videocc >> then: >> required: >> - required-opps >> diff --git a/include/dt-bindings/clock/qcom,x1p42100-videocc.h b/include/dt-bindings/clock/qcom,x1p42100-videocc.h >> new file mode 100644 >> index 0000000000000000000000000000000000000000..eb6c9b7264f8cbced7cfa0001903238ffa168431 >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,x1p42100-videocc.h >> @@ -0,0 +1,21 @@ >> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ >> +/* >> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. >> + */ >> + >> +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H >> +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H >> + >> +#include "qcom,sm8650-videocc.h" >> + >> +/* X1P42100 introduces below new clocks and resets compared to SM8650 */ > > And then someone introduces new clocks or resets into SM8650 bindings > and this gets busted. Please extend the existing header. > Yes, I will drop this and extend the SM8650 bindings to include the new clocks and BCR. Thanks, Jagadeesh >> + >> +/* VIDEO_CC clocks */ >> +#define VIDEO_CC_MVS0_BSE_CLK 17 >> +#define VIDEO_CC_MVS0_BSE_CLK_SRC 18 >> +#define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19 >> + >> +/* VIDEO_CC resets */ >> +#define VIDEO_CC_MVS0_BSE_BCR 8 >> + >> +#endif >> >> -- >> 2.34.1 >> >