Re: [PATCH v7 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space

[Konrad Dybcio <konrad.dybcio@linaro.org>]

On 8.12.2023 15:37, Thomas Gleixner wrote:
> On Mon, Nov 27 2023 at 16:52, Konrad Dybcio wrote:
> 
> The prefix in the subject is wrong. Also please write out register. This
> is not Xitter.
Had a feeling it would be too long, but actually it'd be perfect
72 chars :)

> 
>> The MPM hardware is accessible to us from the ARM CPUs through a shared
> 
> to us? Can you access that hardware? I doubt it.
With a small enough "stick".. but I get your point

> 
> Please use neutral tone as documented in Documentation/process/
> 
>> memory region (RPM MSG RAM) that's also concurrently accessed by other
>> kinds of cores on the system (like modem, ADSP etc.). Modeling this
>> relation in a (somewhat) sane manner in the device tree basically
>> requires us to either present the MPM as a child of said memory region
>> (which makes little sense, as a mapped memory carveout is not a bus),
>> define nodes which bleed their register spaces into one another, or
>> passing their slice of the MSG RAM through some kind of a property.
>>
>> Go with the third option and add a way to map a region passed through
>> the "qcom,rpm-msg-ram" property as our register space.
>>
>> The current way of using 'reg' is preserved for ABI reasons.
> 
> It's not an ABI reason. It's backwards compatibility with old device
> trees, right?
Yes, I thought of something else.

> 
> I'll fix it up for you this time. No need to resend.
Thanks!

Konrad