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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id s18sm15016292wmc.41.2019.05.20.04.26.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 20 May 2019 04:26:49 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 0/7] clk: meson: fix mpll jitter From: Jerome Brunet To: Neil Armstrong , Michael Turquette , Stephen Boyd Cc: Kevin Hilman , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 20 May 2019 13:26:48 +0200 In-Reply-To: <20190513123115.18145-1-jbrunet@baylibre.com> References: <20190513123115.18145-1-jbrunet@baylibre.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.30.5 (3.30.5-1.fc29) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 2019-05-13 at 14:31 +0200, Jerome Brunet wrote: > This patchset is a squash of these previous patchsets [0], [1] without > modification, beside a re-ordering of the changes to facilitate backports > > We are observing a lot of jitter on the MPLL outputs of the g12a. > No such jitter is seen on gx family. On the axg family, only MPLL2 > seems affected. This was not a problem so far since this MPLL output > is not used. > > The jitter can be as high as +/- 4%. > > This is a problem for audio application. This may cause distortion on > i2s and completely break SPDIF. > > After exchanging with Amlogic, it seems we have activated (by mistake) > the 'spread spectrum' feature. > > The 3 first patches properly set the bit responsible for the spread > spectrum in the mpll driver and add the required correction in the > related clock controllers. > > When the g12a support has been initially submitted, the MPLL appeared > (overall) fine. At the time, the board I used was flashed with Amlogic > vendor u-boot. Since then, I moved to an early version on mainline > u-boot, which is likely to initialize the clock differently. > > While debugging audio support, I noticed that MPLL based clocks were way > above target. It appeared the fractional part of the divider was not > working. > > To work properly, the MPLLs each needs an initial setting in addition to > a common one. No one likes those register sequences but sometimes, like > here for PLL clocks, there is no way around it. > > The last 4 patches add the possibility to set initial register sequence > for the ee clock controller and the MPLL driver. It is then used to enable > the fractional part of the g12a MPLL. > > As agreed with the clock maintainers, I'll submit a series to CCF to > remove the .init() callbacks and introduce register()/deregister() > callbacks later on (pinky swear). > > Jerome Brunet (7): > clk: meson: mpll: properly handle spread spectrum > clk: meson: gxbb: no spread spectrum on mpll0 > clk: meson: axg: spread spectrum is on mpll2 > clk: meson: mpll: add init callback and regs > clk: meson: g12a: add mpll register init sequences > clk: meson: eeclk: add init regs > clk: meson: g12a: add controller register init > > drivers/clk/meson/axg.c | 10 ++++----- > drivers/clk/meson/clk-mpll.c | 36 ++++++++++++++++++++++++--------- > drivers/clk/meson/clk-mpll.h | 3 +++ > drivers/clk/meson/g12a.c | 32 ++++++++++++++++++++++++++++- > drivers/clk/meson/gxbb.c | 5 ----- > drivers/clk/meson/meson-eeclk.c | 3 +++ > drivers/clk/meson/meson-eeclk.h | 2 ++ > 7 files changed, 70 insertions(+), 21 deletions(-) > series applied to v5.3/drivers