From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CF02C64E7B for ; Mon, 30 Nov 2020 11:13:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B01C207BC for ; Mon, 30 Nov 2020 11:13:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="DEtXi/tG" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727785AbgK3LNl (ORCPT ); Mon, 30 Nov 2020 06:13:41 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:3205 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725902AbgK3LNk (ORCPT ); Mon, 30 Nov 2020 06:13:40 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 30 Nov 2020 03:13:03 -0800 Received: from [10.26.72.142] (10.124.1.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 30 Nov 2020 11:12:48 +0000 Subject: Re: [PATCH] dmaengine: tegra-apb: fix reference leak in tegra_dma_issue_pending and tegra_dma_synchronize To: Qinglang Miao , Laxman Dewangan , Vinod Koul , Dan Williams , Thierry Reding CC: , , References: <20201127094431.120771-1-miaoqinglang@huawei.com> From: Jon Hunter Message-ID: Date: Mon, 30 Nov 2020 11:12:45 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201127094431.120771-1-miaoqinglang@huawei.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606734783; bh=lcK1YEl/L4MjUjqxhnW4k9aJmOIQTqHyqj06Q0RHP44=; h=Subject:To:CC:References:From:Message-ID:Date:User-Agent: MIME-Version:In-Reply-To:Content-Type:Content-Language: Content-Transfer-Encoding:X-Originating-IP:X-ClientProxiedBy; b=DEtXi/tG6kC58tw1ZuacwKWGo+iXVKxDmmpsOwQ3kvJAbRttpcvB67IWOjwY91L5r I40RfErKGaO6ruhTvW5bQXrfK7rqIsFSF+dGVPnkPTxt5lSONG1zROIZySaeC3aBPz cEGR6CVt2FqZd+rxmL8xNUjEyRL+41qMFNRNFFI3y58mW6Q8YW/T7wfQjSJCs3yEeB Y+8s59VZECNFx/GymDRUrzTd66yK11CtJZzLeSV5+6i/1SI2e2VRgY3BXRHMDuvAgD CzlAlVa0w+1eucmF8/6ustl1YzsQd7jgwA7CRrMcC0FNhOSe+VlSY0fPLO0ls+G7nU dDcrQSjIDlsFA== Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27/11/2020 09:44, Qinglang Miao wrote: > pm_runtime_get_sync will increment pm usage counter even it > failed. Forgetting to putting operation will result in a > reference leak here. > > A new function pm_runtime_resume_and_get is introduced in > [0] to keep usage counter balanced. So We fix the reference > leak by replacing it with new funtion. > > [0] dd8088d5a896 ("PM: runtime: Add pm_runtime_resume_and_get to deal with usage counter") > > Fixes: 84a3f375eea9 ("dmaengine: tegra-apb: Keep clock enabled only during of DMA transfer") > Fixes: 664475cffb8c ("dmaengine: tegra-apb: Ensure that clock is enabled during of DMA synchronization") > Reported-by: Hulk Robot > Signed-off-by: Qinglang Miao > --- > drivers/dma/tegra20-apb-dma.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c > index 71827d9b0..b7260749e 100644 > --- a/drivers/dma/tegra20-apb-dma.c > +++ b/drivers/dma/tegra20-apb-dma.c > @@ -723,7 +723,7 @@ static void tegra_dma_issue_pending(struct dma_chan *dc) > goto end; > } > if (!tdc->busy) { > - err = pm_runtime_get_sync(tdc->tdma->dev); > + err = pm_runtime_resume_and_get(tdc->tdma->dev); > if (err < 0) { > dev_err(tdc2dev(tdc), "Failed to enable DMA\n"); > goto end; > @@ -818,7 +818,7 @@ static void tegra_dma_synchronize(struct dma_chan *dc) > struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); > int err; > > - err = pm_runtime_get_sync(tdc->tdma->dev); > + err = pm_runtime_resume_and_get(tdc->tdma->dev); > if (err < 0) { > dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err); > return; Reviewed-by: Jon Hunter Cheers Jon -- nvpublic