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boundary="------------040A0P0AYqQQTKmEMrnbxBH0"; protected-headers="v1" From: Matt Coster To: Alexandru Dadu Cc: Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Message-ID: Subject: Re: [PATCH v2] drm/imagination: loop counters moved to loop scope References: <20250402-for-loop-counter-scope-v2-1-4fd550d22832@imgtec.com> In-Reply-To: <20250402-for-loop-counter-scope-v2-1-4fd550d22832@imgtec.com> --------------040A0P0AYqQQTKmEMrnbxBH0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 02/04/2025 09:40, Alexandru Dadu wrote: > Reduce the scope of some loop counters as these aren't needed outside > the loops they're used in. >=20 > Signed-off-by: Alexandru Dadu Hi Alexandru, Thanks for dragging us into the bright, bright future of (C)99! Reviewed-by: Matt Coster I'll apply this to drm-misc-next on Monday if nobody has any objections. Cheers, Matt > --- > Changes in v2: > - Remove a loop counter variable definition > - Link to v1: https://lore.kernel.org/r/20250401-for-loop-counter-scope= -v1-1-5ba75770be52@imgtec.com > --- > drivers/gpu/drm/imagination/pvr_debugfs.c | 3 +-- > drivers/gpu/drm/imagination/pvr_free_list.c | 3 +-- > drivers/gpu/drm/imagination/pvr_fw.c | 12 ++++-------- > drivers/gpu/drm/imagination/pvr_fw_meta.c | 3 +-- > drivers/gpu/drm/imagination/pvr_fw_mips.c | 6 ++---- > drivers/gpu/drm/imagination/pvr_fw_trace.c | 23 ++++++++-------------= -- > drivers/gpu/drm/imagination/pvr_gem.c | 4 +--- > drivers/gpu/drm/imagination/pvr_hwrt.c | 12 ++++-------- > drivers/gpu/drm/imagination/pvr_stream.c | 12 ++++-------- > drivers/gpu/drm/imagination/pvr_vm_mips.c | 3 +-- > 10 files changed, 27 insertions(+), 54 deletions(-) >=20 > diff --git a/drivers/gpu/drm/imagination/pvr_debugfs.c b/drivers/gpu/dr= m/imagination/pvr_debugfs.c > index 6b77c9b4bde880cac6606764952d14be6c30b230..c7ce7daaa87a09b1c8e79f3= 91e54b93642f0cb26 100644 > --- a/drivers/gpu/drm/imagination/pvr_debugfs.c > +++ b/drivers/gpu/drm/imagination/pvr_debugfs.c > @@ -28,9 +28,8 @@ pvr_debugfs_init(struct drm_minor *minor) > struct drm_device *drm_dev =3D minor->dev; > struct pvr_device *pvr_dev =3D to_pvr_device(drm_dev); > struct dentry *root =3D minor->debugfs_root; > - size_t i; >=20 > - for (i =3D 0; i < ARRAY_SIZE(pvr_debugfs_entries); ++i) { > + for (size_t i =3D 0; i < ARRAY_SIZE(pvr_debugfs_entries); ++i) = { > const struct pvr_debugfs_entry *entry =3D &pvr_debugfs_= entries[i]; > struct dentry *dir; >=20 > diff --git a/drivers/gpu/drm/imagination/pvr_free_list.c b/drivers/gpu/= drm/imagination/pvr_free_list.c > index 5e51bc980751c9e84f5365b633a22540426631ee..5228e214491c6217965a465= dd91d52bd2a0b8945 100644 > --- a/drivers/gpu/drm/imagination/pvr_free_list.c > +++ b/drivers/gpu/drm/imagination/pvr_free_list.c > @@ -237,11 +237,10 @@ pvr_free_list_insert_pages_locked(struct pvr_free= _list *free_list, > dma_addr_t dma_addr =3D sg_page_iter_dma_address(&dma_i= ter); > u64 dma_pfn =3D dma_addr >> > ROGUE_BIF_PM_PHYSICAL_PAGE_ALIGNSHIFT; > - u32 dma_addr_offset; >=20 > BUILD_BUG_ON(ROGUE_BIF_PM_PHYSICAL_PAGE_SIZE > PAGE_SIZ= E); >=20 > - for (dma_addr_offset =3D 0; dma_addr_offset < PAGE_SIZE= ; > + for (u32 dma_addr_offset =3D 0; dma_addr_offset < PAGE_= SIZE; > dma_addr_offset +=3D ROGUE_BIF_PM_PHYSICAL_PAGE_SI= ZE) { > WARN_ON_ONCE(dma_pfn >> 32); >=20 > diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/ima= gination/pvr_fw.c > index 3debc9870a82ae7de9b2dc173df84c466c137bb3..d43efa8810b80f77edde8a6= 901317e43e629b4b3 100644 > --- a/drivers/gpu/drm/imagination/pvr_fw.c > +++ b/drivers/gpu/drm/imagination/pvr_fw.c > @@ -50,9 +50,8 @@ pvr_fw_find_layout_entry(struct pvr_device *pvr_dev, = enum pvr_fw_section_id id) > { > const struct pvr_fw_layout_entry *layout_entries =3D pvr_dev->f= w_dev.layout_entries; > u32 num_layout_entries =3D pvr_dev->fw_dev.header->layout_entry= _num; > - u32 entry; >=20 > - for (entry =3D 0; entry < num_layout_entries; entry++) { > + for (u32 entry =3D 0; entry < num_layout_entries; entry++) { > if (layout_entries[entry].id =3D=3D id) > return &layout_entries[entry]; > } > @@ -65,9 +64,8 @@ pvr_fw_find_private_data(struct pvr_device *pvr_dev) > { > const struct pvr_fw_layout_entry *layout_entries =3D pvr_dev->f= w_dev.layout_entries; > u32 num_layout_entries =3D pvr_dev->fw_dev.header->layout_entry= _num; > - u32 entry; >=20 > - for (entry =3D 0; entry < num_layout_entries; entry++) { > + for (u32 entry =3D 0; entry < num_layout_entries; entry++) { > if (layout_entries[entry].id =3D=3D META_PRIVATE_DATA |= | > layout_entries[entry].id =3D=3D MIPS_PRIVATE_DATA |= | > layout_entries[entry].id =3D=3D RISCV_PRIVATE_DATA)= > @@ -97,7 +95,6 @@ pvr_fw_validate(struct pvr_device *pvr_dev) > const u8 *fw =3D firmware->data; > u32 fw_offset =3D firmware->size - SZ_4K; > u32 layout_table_size; > - u32 entry; >=20 > if (firmware->size < SZ_4K || (firmware->size % FW_BLOCK_SIZE))= > return -EINVAL; > @@ -144,7 +141,7 @@ pvr_fw_validate(struct pvr_device *pvr_dev) > return -EINVAL; >=20 > layout_entries =3D (const struct pvr_fw_layout_entry *)&fw[fw_o= ffset]; > - for (entry =3D 0; entry < header->layout_entry_num; entry++) { > + for (u32 entry =3D 0; entry < header->layout_entry_num; entry++= ) { > u32 start_addr =3D layout_entries[entry].base_addr; > u32 end_addr =3D start_addr + layout_entries[entry].all= oc_size; >=20 > @@ -233,13 +230,12 @@ pvr_fw_find_mmu_segment(struct pvr_device *pvr_de= v, u32 addr, u32 size, void *fw > const struct pvr_fw_layout_entry *layout_entries =3D pvr_dev->f= w_dev.layout_entries; > u32 num_layout_entries =3D pvr_dev->fw_dev.header->layout_entry= _num; > u32 end_addr =3D addr + size; > - int entry =3D 0; >=20 > /* Ensure requested range is not zero, and size is not causing = addr to overflow. */ > if (end_addr <=3D addr) > return -EINVAL; >=20 > - for (entry =3D 0; entry < num_layout_entries; entry++) { > + for (int entry =3D 0; entry < num_layout_entries; entry++) { > u32 entry_start_addr =3D layout_entries[entry].base_add= r; > u32 entry_end_addr =3D entry_start_addr + layout_entrie= s[entry].alloc_size; >=20 > diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/dr= m/imagination/pvr_fw_meta.c > index c39beb70c3173ebdab13b4e810ce5d9a3419f0ba..d8004a56b1f4e29be3a773a= 41a7ffd74c14c5786 100644 > --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c > +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c > @@ -370,13 +370,12 @@ configure_seg_mmu(struct pvr_device *pvr_dev, u32= **boot_conf_ptr) > const struct pvr_fw_layout_entry *layout_entries =3D pvr_dev->f= w_dev.layout_entries; > u32 num_layout_entries =3D pvr_dev->fw_dev.header->layout_entry= _num; > u64 seg_out_addr_top; > - u32 i; >=20 > seg_out_addr_top =3D > ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWP= RIV, > ROGUE_FW_SEGMMU_META_BI= FDM_ID); >=20 > - for (i =3D 0; i < num_layout_entries; i++) { > + for (u32 i =3D 0; i < num_layout_entries; i++) { > /* > * FW code is using the bootloader segment which is alr= eady > * configured on boot. FW coremem code and data don't u= se the > diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/dr= m/imagination/pvr_fw_mips.c > index 0bed0257e2ab75f66d8b8966b2ceac6342396fb5..ee0735b745a9ff5c99637c2= cb312998679f47fd3 100644 > --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c > +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c > @@ -37,10 +37,9 @@ process_elf_command_stream(struct pvr_device *pvr_de= v, const u8 *fw, u8 *fw_code > struct elf32_hdr *header =3D (struct elf32_hdr *)fw; > struct elf32_phdr *program_header =3D (struct elf32_phdr *)(fw = + header->e_phoff); > struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); > - u32 entry; > int err; >=20 > - for (entry =3D 0; entry < header->e_phnum; entry++, program_hea= der++) { > + for (u32 entry =3D 0; entry < header->e_phnum; entry++, program= _header++) { > void *write_addr; >=20 > /* Only consider loadable entries in the ELF segment ta= ble */ > @@ -97,7 +96,6 @@ pvr_mips_fw_process(struct pvr_device *pvr_dev, const= u8 *fw, > const struct pvr_fw_layout_entry *stack_entry; > struct rogue_mipsfw_boot_data *boot_data; > dma_addr_t dma_addr; > - u32 page_nr; > int err; >=20 > err =3D process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw= _data_ptr, fw_core_code_ptr, > @@ -132,7 +130,7 @@ pvr_mips_fw_process(struct pvr_device *pvr_dev, con= st u8 *fw, >=20 > boot_data->reg_base =3D pvr_dev->regs_resource->start; >=20 > - for (page_nr =3D 0; page_nr < ARRAY_SIZE(boot_data->pt_phys_add= r); page_nr++) { > + for (u32 page_nr =3D 0; page_nr < ARRAY_SIZE(boot_data->pt_phys= _addr); page_nr++) { > /* Firmware expects 4k pages, but host page size might = be different. */ > u32 src_page_nr =3D (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4= K) >> PAGE_SHIFT; > u32 page_offset =3D (page_nr * ROGUE_MIPSFW_PAGE_SIZE_4= K) & ~PAGE_MASK; > diff --git a/drivers/gpu/drm/imagination/pvr_fw_trace.c b/drivers/gpu/d= rm/imagination/pvr_fw_trace.c > index 73707daa4e52d13fd1388cb2e9feff0aea109620..74b4c21ea69fbc4f2a97a5b= 283a71ffed88f0882 100644 > --- a/drivers/gpu/drm/imagination/pvr_fw_trace.c > +++ b/drivers/gpu/drm/imagination/pvr_fw_trace.c > @@ -21,7 +21,6 @@ tracebuf_ctrl_init(void *cpu_ptr, void *priv) > { > struct rogue_fwif_tracebuf *tracebuf_ctrl =3D cpu_ptr; > struct pvr_fw_trace *fw_trace =3D priv; > - u32 thread_nr; >=20 > tracebuf_ctrl->tracebuf_size_in_dwords =3D ROGUE_FW_TRACE_BUF_D= EFAULT_SIZE_IN_DWORDS; > tracebuf_ctrl->tracebuf_flags =3D 0; > @@ -31,7 +30,7 @@ tracebuf_ctrl_init(void *cpu_ptr, void *priv) > else > tracebuf_ctrl->log_type =3D ROGUE_FWIF_LOG_TYPE_NONE; >=20 > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; thread_nr++) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); thread_nr++) { > struct rogue_fwif_tracebuf_space *tracebuf_space =3D > &tracebuf_ctrl->tracebuf[thread_nr]; > struct pvr_fw_trace_buffer *trace_buffer =3D &fw_trace-= >buffers[thread_nr]; > @@ -48,10 +47,9 @@ int pvr_fw_trace_init(struct pvr_device *pvr_dev) > { > struct pvr_fw_trace *fw_trace =3D &pvr_dev->fw_dev.fw_trace; > struct drm_device *drm_dev =3D from_pvr_device(pvr_dev); > - u32 thread_nr; > int err; >=20 > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; thread_nr++) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); thread_nr++) { > struct pvr_fw_trace_buffer *trace_buffer =3D &fw_trace-= >buffers[thread_nr]; >=20 > trace_buffer->buf =3D > @@ -88,7 +86,7 @@ int pvr_fw_trace_init(struct pvr_device *pvr_dev) > BUILD_BUG_ON(ARRAY_SIZE(fw_trace->tracebuf_ctrl->tracebuf) !=3D= > ARRAY_SIZE(fw_trace->buffers)); >=20 > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; thread_nr++) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); thread_nr++) { > struct rogue_fwif_tracebuf_space *tracebuf_space =3D > &fw_trace->tracebuf_ctrl->tracebuf[thread_nr]; > struct pvr_fw_trace_buffer *trace_buffer =3D &fw_trace-= >buffers[thread_nr]; > @@ -99,7 +97,7 @@ int pvr_fw_trace_init(struct pvr_device *pvr_dev) > return 0; >=20 > err_free_buf: > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; thread_nr++) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); thread_nr++) { > struct pvr_fw_trace_buffer *trace_buffer =3D &fw_trace-= >buffers[thread_nr]; >=20 > if (trace_buffer->buf) > @@ -112,9 +110,8 @@ int pvr_fw_trace_init(struct pvr_device *pvr_dev) > void pvr_fw_trace_fini(struct pvr_device *pvr_dev) > { > struct pvr_fw_trace *fw_trace =3D &pvr_dev->fw_dev.fw_trace; > - u32 thread_nr; >=20 > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; thread_nr++) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); thread_nr++) { > struct pvr_fw_trace_buffer *trace_buffer =3D &fw_trace-= >buffers[thread_nr]; >=20 > pvr_fw_object_unmap_and_destroy(trace_buffer->buf_obj);= > @@ -184,9 +181,7 @@ struct pvr_fw_trace_seq_data { >=20 > static u32 find_sfid(u32 id) > { > - u32 i; > - > - for (i =3D 0; i < ARRAY_SIZE(stid_fmts); i++) { > + for (u32 i =3D 0; i < ARRAY_SIZE(stid_fmts); i++) { > if (stid_fmts[i].id =3D=3D id) > return i; > } > @@ -285,12 +280,11 @@ static void fw_trace_get_first(struct pvr_fw_trac= e_seq_data *trace_seq_data) > static void *fw_trace_seq_start(struct seq_file *s, loff_t *pos) > { > struct pvr_fw_trace_seq_data *trace_seq_data =3D s->private; > - u32 i; >=20 > /* Reset trace index, then advance to *pos. */ > fw_trace_get_first(trace_seq_data); >=20 > - for (i =3D 0; i < *pos; i++) { > + for (u32 i =3D 0; i < *pos; i++) { > if (!fw_trace_get_next(trace_seq_data)) > return NULL; > } > @@ -455,12 +449,11 @@ void > pvr_fw_trace_debugfs_init(struct pvr_device *pvr_dev, struct dentry *d= ir) > { > struct pvr_fw_trace *fw_trace =3D &pvr_dev->fw_dev.fw_trace; > - u32 thread_nr; >=20 > static_assert(ARRAY_SIZE(fw_trace->buffers) <=3D 10, > "The filename buffer is only large enough for a s= ingle-digit thread count"); >=20 > - for (thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buffers)= ; ++thread_nr) { > + for (u32 thread_nr =3D 0; thread_nr < ARRAY_SIZE(fw_trace->buff= ers); ++thread_nr) { > char filename[8]; >=20 > snprintf(filename, ARRAY_SIZE(filename), "trace_%u", th= read_nr); > diff --git a/drivers/gpu/drm/imagination/pvr_gem.c b/drivers/gpu/drm/im= agination/pvr_gem.c > index 6a8c81fe8c1e85c2130a4fe90fce35b6a2be35aa..f936fc7d4e4d16fabe7836e= 4b053de6a11d3577e 100644 > --- a/drivers/gpu/drm/imagination/pvr_gem.c > +++ b/drivers/gpu/drm/imagination/pvr_gem.c > @@ -76,8 +76,6 @@ pvr_gem_object_flags_validate(u64 flags) > DRM_PVR_BO_ALLOW_CPU_USERSPACE_ACCESS), > }; >=20 > - int i; > - > /* > * Check for bits set in undefined regions. Reserved regions re= fer to > * options that can only be set by the kernel. These are explic= itly > @@ -91,7 +89,7 @@ pvr_gem_object_flags_validate(u64 flags) > * Check for all combinations of flags marked as invalid in the= array > * above. > */ > - for (i =3D 0; i < ARRAY_SIZE(invalid_combinations); ++i) { > + for (int i =3D 0; i < ARRAY_SIZE(invalid_combinations); ++i) { > u64 combo =3D invalid_combinations[i]; >=20 > if ((flags & combo) =3D=3D combo) > diff --git a/drivers/gpu/drm/imagination/pvr_hwrt.c b/drivers/gpu/drm/i= magination/pvr_hwrt.c > index 54f88d6c01e565f4f0d1bd4fcc7e2983914b9141..dc0c25fa184700992c8e986= 466a2020e4b2ad355 100644 > --- a/drivers/gpu/drm/imagination/pvr_hwrt.c > +++ b/drivers/gpu/drm/imagination/pvr_hwrt.c > @@ -44,13 +44,12 @@ hwrt_init_kernel_structure(struct pvr_file *pvr_fil= e, > { > struct pvr_device *pvr_dev =3D pvr_file->pvr_dev; > int err; > - int i; >=20 > hwrt->pvr_dev =3D pvr_dev; > hwrt->max_rts =3D args->layers; >=20 > /* Get pointers to the free lists */ > - for (i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > + for (int i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > hwrt->free_lists[i] =3D pvr_free_list_lookup(pvr_file, = args->free_list_handles[i]); > if (!hwrt->free_lists[i]) { > err =3D -EINVAL; > @@ -67,7 +66,7 @@ hwrt_init_kernel_structure(struct pvr_file *pvr_file,= > return 0; >=20 > err_put_free_lists: > - for (i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > + for (int i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > pvr_free_list_put(hwrt->free_lists[i]); > hwrt->free_lists[i] =3D NULL; > } > @@ -78,9 +77,7 @@ hwrt_init_kernel_structure(struct pvr_file *pvr_file,= > static void > hwrt_fini_kernel_structure(struct pvr_hwrt_dataset *hwrt) > { > - int i; > - > - for (i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > + for (int i =3D 0; i < ARRAY_SIZE(hwrt->free_lists); i++) { > pvr_free_list_put(hwrt->free_lists[i]); > hwrt->free_lists[i] =3D NULL; > } > @@ -363,13 +360,12 @@ hwrt_data_init_fw_structure(struct pvr_file *pvr_= file, > struct drm_pvr_create_hwrt_geom_data_args *geom_data_args =3D &= args->geom_data_args; > struct pvr_device *pvr_dev =3D pvr_file->pvr_dev; > struct rogue_fwif_rta_ctl *rta_ctl; > - int free_list_i; > int err; >=20 > pvr_fw_object_get_fw_addr(hwrt->common_fw_obj, > &hwrt_data->data.hwrt_data_common_fw_= addr); >=20 > - for (free_list_i =3D 0; free_list_i < ARRAY_SIZE(hwrt->free_lis= ts); free_list_i++) { > + for (int free_list_i =3D 0; free_list_i < ARRAY_SIZE(hwrt->free= _lists); free_list_i++) { > pvr_fw_object_get_fw_addr(hwrt->free_lists[free_list_i]= ->fw_obj, > &hwrt_data->data.freelists_fw= _addr[free_list_i]); > } > diff --git a/drivers/gpu/drm/imagination/pvr_stream.c b/drivers/gpu/drm= /imagination/pvr_stream.c > index 975336a4facfd0472958c72683ed1a302f7144a1..679aa618b7a9cd2853c7f58= 0e326461c58b535bb 100644 > --- a/drivers/gpu/drm/imagination/pvr_stream.c > +++ b/drivers/gpu/drm/imagination/pvr_stream.c > @@ -67,9 +67,8 @@ pvr_stream_process_1(struct pvr_device *pvr_dev, cons= t struct pvr_stream_def *st > u8 *dest, u32 dest_size, u32 *stream_offset_out) > { > int err =3D 0; > - u32 i; >=20 > - for (i =3D 0; i < nr_entries; i++) { > + for (u32 i =3D 0; i < nr_entries; i++) { > if (stream_def[i].offset >=3D dest_size) { > err =3D -EINVAL; > break; > @@ -131,7 +130,6 @@ pvr_stream_process_ext_stream(struct pvr_device *pv= r_dev, > u32 musthave_masks[PVR_STREAM_EXTHDR_TYPE_MAX]; > u32 ext_header; > int err =3D 0; > - u32 i; >=20 > /* Copy "must have" mask from device. We clear this as we proce= ss the stream. */ > memcpy(musthave_masks, pvr_dev->stream_musthave_quirks[cmd_defs= ->type], > @@ -159,7 +157,7 @@ pvr_stream_process_ext_stream(struct pvr_device *pv= r_dev, >=20 > musthave_masks[type] &=3D ~data; >=20 > - for (i =3D 0; i < header->ext_streams_num; i++) { > + for (u32 i =3D 0; i < header->ext_streams_num; i++) { > const struct pvr_stream_ext_def *ext_def =3D &h= eader->ext_streams[i]; >=20 > if (!(ext_header & ext_def->header_mask)) > @@ -181,7 +179,7 @@ pvr_stream_process_ext_stream(struct pvr_device *pv= r_dev, > * Verify that "must have" mask is now zero. If it isn't then o= ne of the "must have" quirks > * for this command was not present. > */ > - for (i =3D 0; i < cmd_defs->ext_nr_headers; i++) { > + for (u32 i =3D 0; i < cmd_defs->ext_nr_headers; i++) { > if (musthave_masks[i]) > return -EINVAL; > } > @@ -245,13 +243,11 @@ pvr_stream_process(struct pvr_device *pvr_dev, co= nst struct pvr_stream_cmd_defs > if (err) > return err; > } else { > - u32 i; > - > /* > * If we don't have an extension stream then there must= not be any "must have" > * quirks for this command. > */ > - for (i =3D 0; i < cmd_defs->ext_nr_headers; i++) { > + for (u32 i =3D 0; i < cmd_defs->ext_nr_headers; i++) { > if (pvr_dev->stream_musthave_quirks[cmd_defs->t= ype][i]) > return -EINVAL; > } > diff --git a/drivers/gpu/drm/imagination/pvr_vm_mips.c b/drivers/gpu/dr= m/imagination/pvr_vm_mips.c > index 94af854547d6c52471527b6388086a8f7a35aef4..5847a1c92bea8b0923628ad= 7b72913e8977d4b97 100644 > --- a/drivers/gpu/drm/imagination/pvr_vm_mips.c > +++ b/drivers/gpu/drm/imagination/pvr_vm_mips.c > @@ -100,10 +100,9 @@ pvr_vm_mips_fini(struct pvr_device *pvr_dev) > { > struct pvr_fw_device *fw_dev =3D &pvr_dev->fw_dev; > struct pvr_fw_mips_data *mips_data =3D fw_dev->processor_data.m= ips_data; > - int page_nr; >=20 > vunmap(mips_data->pt); > - for (page_nr =3D PVR_MIPS_PT_PAGE_COUNT - 1; page_nr >=3D 0; pa= ge_nr--) { > + for (int page_nr =3D PVR_MIPS_PT_PAGE_COUNT - 1; page_nr >=3D 0= ; page_nr--) { > dma_unmap_page(from_pvr_device(pvr_dev)->dev, > mips_data->pt_dma_addr[page_nr], PAGE_SI= ZE, DMA_TO_DEVICE); >=20 >=20 > --- > base-commit: 2f9d51740cc30e0d2c8a23a55b1e20cf2513c250 > change-id: 20250401-for-loop-counter-scope-115373392913 >=20 > Best regards, > -- > Alexandru Dadu >=20 --=20 Matt Coster E: matt.coster@imgtec.com --------------040A0P0AYqQQTKmEMrnbxBH0-- --------------90fxWH52m5CqqococGL0K0Oe Content-Type: application/pgp-signature; name="OpenPGP_signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="OpenPGP_signature.asc" -----BEGIN PGP SIGNATURE----- wnsEABYIACMWIQS4qDmoJvwmKhjY+nN5vBnz2d5qsAUCZ++yYgUDAAAAAAAKCRB5vBnz2d5qsGfr AP0SJs7ntFio9QDFaTEievp2Kd09VaJZxuUTmcJTLOFDYQD7Bq13jUx8wVwYm+Wfz1z8MseGjXNG 45auCvyQae0J3gc= =aPue -----END PGP SIGNATURE----- --------------90fxWH52m5CqqococGL0K0Oe--