From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61FD9A59; Mon, 28 Oct 2024 11:33:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730115201; cv=none; b=S0iefcoJyIg/7PdCchnUqPU+rsSHVbAeghdim+94hRPN7IDn/YwQXCX2pgUA+KLQhyu8G0QpBLaIqe/Ok4nL7MJL6hNbRB4VZSvwt3O+IglBKvkVftKyvz7022Hk99vYqDdTqsf9Zj937xv+Papnk6bxeQXdbyF2afb0BTJ7tmc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730115201; c=relaxed/simple; bh=pVV6srachtafwwlBUnY7lawnsqiQatUuDFNTiMZlZhs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=RerfssAg4bdCHLrJPNUORFrDKHasBqcknMIqrageM+wDoN4rGpouOLrXhsGJxSUP+RvyTRqLBkMcsFQcgKmgvO29PvyygM5AZEGMT0HyJZI8hAKvmlchWXE0b09AUqbCLvlg28Djo9wXYtqDUNElZo9BvNbUQGrbcbfvz5NnMTQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XVMd61mX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XVMd61mX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52824C4CEC3; Mon, 28 Oct 2024 11:33:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730115200; bh=pVV6srachtafwwlBUnY7lawnsqiQatUuDFNTiMZlZhs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=XVMd61mX2Klh8sbflTgwXt42mcTIJ8iQwjQwiE2E06sW2Em3wbMLLF6PHKvlVNUb7 Yt/8wXL/6gonyjhVEqIlcV6X4jTheO93Eh1UPV1Sped9TPAro0KGa8VsVqh0p8u38T B9UpTbIpsNla6fm5NGhUO15KgUzZJ30tJbuyYDECqOBFAelvC9adgdtqbBSNIc53yr 2JEeXSj9KOsizdkxehxxrcbUsfJvLlZMrKBnXPhkqE7Y0fOtQiMEMicyHOGVa5qcAW xWHJjjh+Gea099J82F14gNDEZaUoHADHmnAaSkc1ZXd7k6TR+CAMoXsitQBX33EMXv hRKs+D8xqC6ag== Message-ID: Date: Mon, 28 Oct 2024 12:33:14 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: qcs615: Add QUPv3 configuration To: Viken Dadhaniya , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_msavaliy@quicinc.com, quic_anupkulk@quicinc.com References: <20241011103346.22925-1-quic_vdadhani@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/10/2024 12:33, Viken Dadhaniya wrote: > Add DT support for QUPv3 Serial Engines. > > Co-developed-by: Mukesh Kumar Savaliya > Signed-off-by: Mukesh Kumar Savaliya > Signed-off-by: Viken Dadhaniya > --- > > Build Dependencies: > > Base: > https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-5-e37617e91c62@quicinc.com/ > https://lore.kernel.org/linux-devicetree/20240926-add_initial_support_for_qcs615-v3-6-e37617e91c62@quicinc.com/ > > Clock: https://lore.kernel.org/linux-devicetree/20240920-qcs615-clock-driver-v2-3-2f6de44eb2aa@quicinc.com/ > ICC: https://lore.kernel.org/linux-devicetree/20240924143958.25-2-quic_rlaggysh@quicinc.com/ > Apps SMMU: https://lore.kernel.org/all/20241011063112.19087-1-quic_qqzhou@quicinc.com/ > --- > arch/arm64/boot/dts/qcom/qcs615.dtsi | 602 ++++++++++++++++++++++++++- > 1 file changed, 598 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi > index 865ead601f85..9d7fc6fc5c6e 100644 > --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi > @@ -5,6 +5,7 @@ > > #include > #include > +#include > #include > #include > #include > @@ -17,6 +18,21 @@ > #address-cells = <2>; > #size-cells = <2>; > > + aliases { > + i2c1 = &i2c1; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c4 = &i2c4; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + i2c7 = &i2c7; > + spi2 = &spi2; > + spi4 = &spi4; > + spi6 = &spi6; > + spi7 = &spi7; > + serial0 = &uart0; Bus aliases are not supposed to be specific to SoC. Drop them from SoC DTSI. > + }; > + > cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -296,6 +312,25 @@ > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + qup_opp_table: opp-table-qup { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > @@ -392,6 +427,24 @@ > #size-cells = <1>; > }; > > + gpi_dma0: qcom,gpi-dma@800000 { That's again downstream code. Do not send us stuff from downstream. Best regards, Krzysztof