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Miller" , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Biao Huang , Maxime Coquelin , Alexandre Torgue , Eric Dumazet Cc: kernel@collabora.com, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Date: Wed, 21 Oct 2026 12:36:37 +0200 In-Reply-To: <34608ab8-18f3-4680-8276-cd8611c05cb1@bootlin.com> References: <20261016-dwmac-mediatek-mt8189-v3-0-25daf2bbcf35@collabora.com> <20261016-dwmac-mediatek-mt8189-v3-5-25daf2bbcf35@collabora.com> <34608ab8-18f3-4680-8276-cd8611c05cb1@bootlin.com> Organization: Collabora Ltd Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.60.2 (3.60.2-2.fc44) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-ZohoMailClient: External Hi Maxime, On Fri, 2026-10-16 at 13:37 +0200, Maxime Chevallier wrote: > Hi Louis-Alexis, >=20 > On 10/16/26 12:31, Louis-Alexis Eyraud wrote: > > In preparation of newer SoC support, that have like MT8189 SoC > > different RX and TX internal delay stage steps than MT8188/MT8195, > > add > > the RX and TX delay stage divider values in the variant platform > > data > > and replace the hardcoded value uses in mt2712_set_delay and > > mt8195_set_delay. > >=20 > > Reviewed-by: Maxime Chevallier > > Signed-off-by: Louis-Alexis Eyraud > > > > --- > > =C2=A0.../net/ethernet/stmicro/stmmac/dwmac-mediatek.c=C2=A0=C2=A0 | 46 > > ++++++++++++++++++---- > > =C2=A01 file changed, 38 insertions(+), 8 deletions(-) > >=20 > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > index 596411d4a5b2..cb5bda53edb9 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c > > @@ -108,6 +108,10 @@ struct mediatek_dwmac_variant { > > =C2=A0 > > =C2=A0 u32 rx_delay_max; > > =C2=A0 u32 tx_delay_max; > > + u16 rx_rmii_delay_stage_div; > > + u16 tx_rmii_delay_stage_div; > > + u16 rx_rgmii_delay_stage_div; > > + u16 tx_rgmii_delay_stage_div; > > =C2=A0 u8 dma_bit_mask; > > =C2=A0}; > > =C2=A0 > > @@ -146,14 +150,22 @@ static int mt2712_set_delay(struct > > mediatek_dwmac_plat_data *plat) > > =C2=A0 u32 fine_val =3D 0; > > =C2=A0 > > =C2=A0 if (phy_interface_mode_is_rgmii(plat->phy_mode)) { > > - rx_delay_stage_div =3D > > MT2712_RGMII_DLY_RXC_STAGE_DIV; > > - tx_delay_stage_div =3D > > MT2712_RGMII_DLY_TXC_STAGE_DIV; > > + rx_delay_stage_div =3D plat->variant- > > >rx_rgmii_delay_stage_div; > > + tx_delay_stage_div =3D plat->variant- > > >tx_rgmii_delay_stage_div; > > =C2=A0 } else { > > - rx_delay_stage_div =3D > > MT2712_RMII_DLY_RXC_STAGE_DIV; > > - tx_delay_stage_div =3D > > MT2712_RMII_DLY_TXC_STAGE_DIV; > > + rx_delay_stage_div =3D plat->variant- > > >rx_rmii_delay_stage_div; > > + tx_delay_stage_div =3D plat->variant- > > >tx_rmii_delay_stage_div; >=20 > Looking closer at this, what's RMII delay ? There's no delays in > RMII, and > it's a single clock not a RX and TX clock like RGMII, there's no RMII > TXC/RXC. >=20 You are right, these structures field and define names are wrong for RMII/MII cases. The mediatek,tx-delay-ps and mediatek,rx-delay-ps vendor properties are used by this driver to fine tune different clocks depending on the phy mode: - RX_CLK/TX_CLK in MII - REF_CLK in RMII - TXC/RXC in RGMII I'll fix the fields and define names in next series revision, along the issues the Sashiko reviews found. > I think it's the same as on allwinner, the delay handling has been > mixed-up between > RMII and RGMII in the glue, you should be able to simplify this even > more by > ditching the RMII case. The register fields that the driver sets in RMII or MII mode to tune the needed clock(s) are different than the ones set in RGMII. So I cannot really ditch the case but I'll simplify the delay handling. For instance I could use a single divider field per mode, since for all compatibles the value is the same in both RX and TX. Best regards, Louis-Alexis >=20 > Maxime