Re: [PATCH net 3/3] net: dsa: lantiq_gswip: fix GSWIP_MDIO_PHY_FCONTX_EN value

[Maxime Chevallier <maxime.chevallier@bootlin.com>]

Hi,

On 9/7/26 15:48, Jan Havran (Advantech Czech) wrote:
> Per the GSW145 data sheet, the FCONTX (bits 8:7) and FCONRX (bits 6:5)
> flow-control fields of the PHY_ADDR_n register both encode 00 = AUTO,
> 01 = EN, 10 = reserved, 11 = DIS. GSWIP_MDIO_PHY_FCONTX_EN was 0x0100,
> i.e. field value 10 (the reserved encoding), instead of 0x0080 (01 = EN);
> FCONRX_EN is already 0x0020 (01). Enabling tx flow control therefore wrote
> the reserved value.
> 
> Set FCONTX_EN to 0x0080. The register is shared by all supported parts.
> 
> Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200")
> Signed-off-by: Jan Havran (Advantech Czech) <havran.jan@email.cz>

Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>

Maxime

> ---
>  drivers/net/dsa/lantiq/lantiq_gswip.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h
> index bc3686faad0d6..0b75be14dc109 100644
> --- a/drivers/net/dsa/lantiq/lantiq_gswip.h
> +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h
> @@ -42,7 +42,7 @@
>  #define  GSWIP_MDIO_PHY_FDUP_DIS	0x0600
>  #define  GSWIP_MDIO_PHY_FCONTX_MASK	0x0180
>  #define  GSWIP_MDIO_PHY_FCONTX_AUTO	0x0000
> -#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0100
> +#define  GSWIP_MDIO_PHY_FCONTX_EN	0x0080
>  #define  GSWIP_MDIO_PHY_FCONTX_DIS	0x0180
>  #define  GSWIP_MDIO_PHY_FCONRX_MASK	0x0060
>  #define  GSWIP_MDIO_PHY_FCONRX_AUTO	0x0000