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Wed, 08 Oct 2025 23:10:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF5r/qNCWsxiulxREssg/rKy9mYecqFg1wGhLqe8k6wn9pxBQuJdPqZTt6pMXVlxTHcmetRJw== X-Received: by 2002:a05:6a20:430e:b0:245:4181:e1ff with SMTP id adf61e73a8af0-32da8130c8amr8959274637.14.1759990229985; Wed, 08 Oct 2025 23:10:29 -0700 (PDT) Received: from [10.0.0.3] ([106.222.229.252]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-33b510e904bsm5592569a91.3.2025.10.08.23.10.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 08 Oct 2025 23:10:29 -0700 (PDT) Message-ID: Date: Thu, 9 Oct 2025 11:40:25 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 7/8] media: iris: move common register definitions to the header Content-Language: en-US To: Dmitry Baryshkov , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251008-iris-sc7280-v1-0-def050ba5e1f@oss.qualcomm.com> <20251008-iris-sc7280-v1-7-def050ba5e1f@oss.qualcomm.com> From: Dikshita Agarwal In-Reply-To: <20251008-iris-sc7280-v1-7-def050ba5e1f@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=ZJzaWH7b c=1 sm=1 tr=0 ts=68e751d7 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=L4UNg9I9cQSOxNpRiiGXlA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Xv1zr1GVMwzzYKxCC1gA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-ORIG-GUID: nfyTJ3iM6HMqILcAMTqKWoTsrd-4kR5y X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfX2dFhi4InPHQq b3jEMX0q/6lHELJT2/H+lgjmn+nATOAgfpgfbtJ3QiBgnFW2qUOlAf/rYI5k/p27iRsoZXWUBTQ CvmmPtQ9711gEfoOeajHn1WCPbiqA/9R5RYd0VAlsY5TyKHYXn/H6N6+dkCeOSZMPFvIc5pAax8 aFU3Sb1A3E4e7HH/Je4AC50zqXc6ak+eKSOAswiDnc2ikWOKp+f83zyZ+lKm8nWq7Om+5DwyXdZ 5p5PV+9v2YNb5g+JKd+t0nt6zcvFfTwPOm/BqX3qIF47hTj/Ia3M1ZQWTpyvdO9JLoRUDjUTQQZ kaDJZVnNCRpFK0eN4Ye4IcnpXHTNF/zaFRax2Fy6RFLFzzIWUx65JiJhkgMB4Ij8Hi8amIaNJlp FUjtrWM5sO/Gs5+pFphnaolNJT5bQA== X-Proofpoint-GUID: nfyTJ3iM6HMqILcAMTqKWoTsrd-4kR5y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-09_01,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote: > Simplify adding new platforms by moving common registers definitions > from VPU 3.x and "common" file to the header with other register > defines. > Similar to https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/ ? Thanks, Dikshita > Signed-off-by: Dmitry Baryshkov > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 35 -------------- > drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 ----------------- > .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++++++ > 3 files changed, 56 insertions(+), 78 deletions(-) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34a53c63c595f72 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -11,48 +11,13 @@ > #include "iris_vpu_common.h" > #include "iris_vpu_register_defines.h" > > -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > -#define AON_BASE_OFFS 0x000E0000 > #define AON_MVP_NOC_RESET 0x0001F000 > > -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > -#define REQ_POWER_DOWN_PREP BIT(0) > -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > -#define CORE_CLK_RUN 0x0 > -/* VPU v3.5 */ > -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) > - > -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > -#define CTL_AXI_CLK_HALT BIT(0) > -#define CTL_CLK_HALT BIT(1) > - > -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > -#define RESET_HIGH BIT(0) > - > -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) > -#define CORE_BRIDGE_SW_RESET BIT(0) > -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) > - > -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > -#define MSK_CORE_POWER_ON BIT(1) > - > #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) > #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) > > #define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) > > -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) > - > -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > - > #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) > #define SW_RESET BIT(0) > #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c > index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8088130fb625fd 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c > @@ -11,13 +11,6 @@ > #include "iris_vpu_common.h" > #include "iris_vpu_register_defines.h" > > -#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > -#define AON_BASE_OFFS 0x000E0000 > - > -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) > - > -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) > -#define CLEAR_XTENSA2HOST_INTR BIT(0) > > #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48) > #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C) > @@ -35,42 +28,6 @@ > #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) > #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) > > -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) > -#define HOST2XTENSA_INTR_ENABLE BIT(0) > - > -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > -#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > -#define MSK_CORE_POWER_ON BIT(1) > - > -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) > -#define CPU_IC_SOFTINT_H2A_SHFT 0x0 > - > -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) > -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) > -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) > - > -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) > -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) > -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) > - > -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > - > -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) > -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > -#define CTL_AXI_CLK_HALT BIT(0) > -#define CTL_CLK_HALT BIT(1) > - > -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > -#define RESET_HIGH BIT(0) > - > -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > -#define REQ_POWER_DOWN_PREP BIT(0) > - > -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > - > static void iris_vpu_interrupt_init(struct iris_core *core) > { > u32 mask_val; > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe8ad445a0a13f4 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h > @@ -9,9 +9,65 @@ > #define VCODEC_BASE_OFFS 0x00000000 > #define CPU_BASE_OFFS 0x000A0000 > #define WRAPPER_BASE_OFFS 0x000B0000 > +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 > +#define AON_BASE_OFFS 0x000E0000 > + > +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) > > #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS) > > +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C) > +#define CLEAR_XTENSA2HOST_INTR BIT(0) > + > +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148) > +#define HOST2XTENSA_INTR_ENABLE BIT(0) > + > +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS) > +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150) > +#define CPU_IC_SOFTINT_H2A_SHFT 0x0 > + > +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) > +#define CORE_BRIDGE_SW_RESET BIT(0) > +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) > + > +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) > +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) > +#define MSK_CORE_POWER_ON BIT(1) > + > +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C) > +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3) > +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2) > + > +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10) > +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3) > +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2) > + > #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) > +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) > +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) > +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) > +#define REQ_POWER_DOWN_PREP BIT(0) > + > +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) > +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ > +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ > +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ > + > +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) > + > +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) > +#define CORE_CLK_RUN 0x0 > + > +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10) > + > +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) > +#define CTL_AXI_CLK_HALT BIT(0) > +#define CTL_CLK_HALT BIT(1) > + > +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) > +#define RESET_HIGH BIT(0) > + > +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) > +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) > > #endif >