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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 16:22:23.7310 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7d8b8ab7-ff79-4099-e8c1-08de59d26ce9 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009526.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR10MB6529 X-Proofpoint-ORIG-GUID: AGLZSeP75Zjv5vGXlBz7Fqz6ixizLjgg X-Proofpoint-GUID: AGLZSeP75Zjv5vGXlBz7Fqz6ixizLjgg X-Authority-Analysis: v=2.4 cv=HbUZjyE8 c=1 sm=1 tr=0 ts=69724ec3 cx=c_pps a=RAmqSNJtJSKe9EuFyr+DeA==:117 a=d6reE3nDawwanmLcZTMRXA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=rg8MelPR9j8A:10 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=gEfo2CItAAAA:8 a=8b9GpE9nAAAA:8 a=vR-eFnANnCulSu6mStMA:9 a=QEXdDO2ut3YA:10 a=sptkURWiP4Gy88Gu7hUp:22 a=T3LWEMljR5ZiDmsYVIUa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIyMDEyNSBTYWx0ZWRfX+Mfxg7FVmjRX COPaCi4S6mAUwBdDLFhW2H7YvZMOdlIbenwUDZflBgbP8ogyvkKVY1R2edjOn+ErzjD0Q8YSLt6 YnYQeX77Jij7xWnlBqYDl49gRRspq/FUskzALzEASbdPm2e0YtUVGI/kMZGkk0Sf6+rml5FdM2U vWdbJ1yFF7awwsQT28pHzSRlF7pxr+55j9MedVXigSv8/sHtufEvk8IxBoeJSAqeKBn0b2UoHm5 mW4O4oVK4uIatJDKLjZTyliCpDkYP4qcC+huQW8jrwxWe5weCKIXjw/mPy8trWYQlq930KvqSkg uSXBxpKh2n2c1ic65QeUPOsm9u5pEqnUblCVcPnt1Krt5sDBN0z5IeVn45lmcxbfHwxupcqcriT 6iIJ6V2yJK+Uw2Lg4C1YLIwZQD5KaLWOQnxcxHAutkIpIkjrLn1q6Ac5qnCgc/SfMKpxxp1dmIQ UGPZSrqQxwm1nXM86Hg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-22_02,2026-01-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 priorityscore=1501 spamscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601220125 On 1/22/26 17:19, Gatien Chevallier wrote: > Document the stm32 debug bus. The debug bus is responsible for > checking the debug sub-system accessibility before probing any related > drivers. > > Signed-off-by: Gatien Chevallier > --- > .../bindings/bus/st,stm32mp131-dbg-bus.yaml | 77 ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > > diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml > new file mode 100644 > index 000000000000..57f01d301e75 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/st,stm32mp131-dbg-bus.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: STM32 Coresight bus > + > +maintainers: > + - Gatien Chevallier > + > +description: > + The STM32 debug bus is in charge of checking the debug configuration > + of the platform before probing the peripheral drivers that rely on the debug > + domain. > + > +properties: > + compatible: > + items: > + - enum: > + - st,stm32mp131-dbg-bus > + - st,stm32mp151-dbg-bus > + > + "#address-cells": > + const: 1 > + > + "#size-cells": > + const: 1 > + > + ranges: true Maybe maxItems:2 is preferred here, no? > + > + reg: > + maxItems: 1 > + > + "#access-controller-cells": > + const: 1 > + description: > + Contains the debug profile necessary to access the peripheral. > + > +patternProperties: > + "^.*@[0-9a-f]+$": > + description: Debug related peripherals > + type: object > + > + additionalProperties: true > + > + required: > + - access-controllers > + > +required: > + - "#access-controller-cells" > + - "#address-cells" > + - "#size-cells" > + - compatible > + - ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + dbg_bus: bus@50080000 { > + compatible = "st,stm32mp131-dbg-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + #access-controller-cells = <1>; > + ranges = <0x50080000 0x50080000 0x3f80000>; > + > + cs_cti_trace: cti@50094000 { > + compatible = "arm,coresight-cti", "arm,primecell"; > + reg = <0x50094000 0x1000>; > + clocks = <&rcc CK_DBG>; > + clock-names = "apb_pclk"; > + access-controllers = <&dbg_bus 0>; > + }; > + }; >