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Mon, 5 Oct 2026 10:44:57 -0500 Received: from [10.24.50.20] (moteen-ubuntu-desk.dhcp.ti.com [10.24.50.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 695Fison1424820; Mon, 5 Oct 2026 10:44:55 -0500 Message-ID: Date: Mon, 5 Oct 2026 21:14:54 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] arm64: dts: ti: Add k3-am62p-wakeup.dtsi for AM62PX efuse GP_SW1 To: Judith Mendez , Nishanth Menon CC: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , References: <20260922165714.425576-1-jm@ti.com> Content-Language: en-US From: Moteen Shah In-Reply-To: <20260922165714.425576-1-jm@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PEPF0000005F:EE_|IA6PR10MB997632:EE_ X-MS-Office365-Filtering-Correlation-Id: 144e9dd3-8765-4c7e-a90c-08df22f7abcc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|82310400026|1800799024|36860700016|10067099003|22082099003|18002099003|13003099007|3023799007|56012099006; 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On 22/09/26 22:27, Judith Mendez wrote: > Create k3-am62p-wakeup.dtsi which includes AM62P-specific WAKEUP > domain nodes. > > In k3-am62p-wakeup.dtsi, add the efuse node for GP_SW1 register at > offset 0x230. GP_SW1 will be used to determine AM62P silicon revision. Nit: Isn't GP_SW1 0x230 + offset? might need fixing of the msg. > > Signed-off-by: Judith Mendez > --- > This patch adds GP_SW1 efuse node for AM62PX only now that bindings [0] > are in place. > > Changes since v1: > - Move gpsw_efuse from k3-am62p-j722s-common-wakeup.dtsi to the new > k3-am62p-wakeup.dtsi [1] since GP_SW efuse registers are marked > reserved for J722S. > > [0] https://lore.kernel.org/all/178942274041.683176.599438200260103620.b4-ty@kernel.org/ > [1] https://lore.kernel.org/all/5d4742fa-e26a-4b49-8eb4-b6291c402334@ti.com/#t > > Link to v1: > https://lore.kernel.org/all/20260915001304.3781247-1-jm@ti.com/ > --- > arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi | 25 +++++++++++++++++++++ > arch/arm64/boot/dts/ti/k3-am62p.dtsi | 1 + > 2 files changed, 26 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi > new file mode 100644 > index 0000000000000..c56fb3890c983 > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: GPL-2.0-only OR MIT > +/* > + * Device Tree file for the AM62P WAKEUP domain peripherals > + * > + * Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/ > + */ > + > +&wkup_conf { > + gpsw_efuse: efuse@230 { > + compatible = "ti,am62p-efuse", "socionext,uniphier-efuse"; > + reg = <0x230 0x10>; > + #address-cells = <1>; > + bootph-all; Nit: I think the property ordering for bootph-all doesn't look correct. With the above two changes, if valid. Reviewed-by: Moteen Shah Regards, Moteen > + #size-cells = <1>; > + > + gpsw1: gpsw1@4 { > + reg = <0x4 0x4>; > + }; > + }; > +}; > + > +&chipid { > + nvmem-cells = <&gpsw1>; > + nvmem-cell-names = "gpsw1"; > +}; > diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi > index 9d6266d6ddb82..058f264ee0646 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi > @@ -154,3 +154,4 @@ cbass_wakeup: bus@b00000 { > > /* Include AM62P specific peripherals */ > #include "k3-am62p-main.dtsi" > +#include "k3-am62p-wakeup.dtsi"