From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDC01326926; Thu, 8 Jan 2026 19:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767900853; cv=none; b=YFDbbvMK5huRdEnZLfpCK7QZGcBxSXjX+gafx5CIqvSpRcE7us9BVt20uiB/4YvmuVtoejkdNCMFf007w/RJBgFx+NkHIREYyrcPEHGdD+K5eWtNpohHcqe0YZpD9RxxJJ9YPRjURynoe2bqHPVN42KCEDJ/ltjljN6TUJx2vm8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1767900853; c=relaxed/simple; bh=i9aLFZyQgucBGaDkhQ0jYWw3FmOXM1KOstV3zoWKFCE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=jN+56AvMx5twk1a3Hxt/YfLYgZCmlYUHL1VA9eYKDu/HMMZPs6OPuI62LcA6Bevyk5HYsc3JPUSnqm1RXWnZN+bfyLab3jyoZDN+YY3nyO9Sd82CN7YEaBciN70Wi2kUr9dTlT6hnMG/GgqjP6jrSECroSOjM8EphuRj++D94Ws= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QAS2k5m9; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QAS2k5m9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1767900852; x=1799436852; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=i9aLFZyQgucBGaDkhQ0jYWw3FmOXM1KOstV3zoWKFCE=; b=QAS2k5m9TetlwzTTMA3vH/WR1sDW6CU05SHaMWI2KHXvkWuYrs4u4CCw R+u7nOkdlOGHxyIZFe/BIEOfyWXaHZZ4dSJiUpy+f4RefSiBKlsdqj/X2 hopQXt3ymcV5yTqwa1Ju2eRwil6DSFutxaWZT/+EnjEKEyVLpT4AnY/q0 OXCIa6eva2fy5i2Rk1Tk8qkdVtwQkV64gYRwRNtazxnV+O+HcLUNbCniw yfp2IS9nCb39EXKFXpuTKWuTZNCPxQsRTVMqXAElPJslIn3g6LaemY7Gb MIlmo9qrVwKiiVZUiBJabLz0rNe1n9zGFBmostfFWMTYsLXSntDi+punh Q==; X-CSE-ConnectionGUID: KJx1xenYT1Cej8Rj4xvSYw== X-CSE-MsgGUID: d9yvVGBTS3eQyyzJpogfQQ== X-IronPort-AV: E=McAfee;i="6800,10657,11665"; a="91949202" X-IronPort-AV: E=Sophos;i="6.21,211,1763452800"; d="scan'208";a="91949202" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2026 11:34:12 -0800 X-CSE-ConnectionGUID: t5a8eRDmTGmtpO4nqRNxRA== X-CSE-MsgGUID: lPNHLSt/Q0uEINkT4tgEiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,211,1763452800"; d="scan'208";a="203309324" Received: from unknown (HELO [10.241.241.30]) ([10.241.241.30]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jan 2026 11:34:12 -0800 Message-ID: Date: Thu, 8 Jan 2026 11:34:11 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] perf/x86/intel: Support newly introduced 4 OMR MSRs for DMR & NVL To: Dapeng Mi , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Falcon Thomas , Xudong Hao References: <20251120053431.491677-1-dapeng1.mi@linux.intel.com> <20251120053431.491677-2-dapeng1.mi@linux.intel.com> Content-Language: en-US From: "Chen, Zide" In-Reply-To: <20251120053431.491677-2-dapeng1.mi@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/19/2025 9:34 PM, Dapeng Mi wrote: > Diamond Rapids and Nova Lake feature an expanded facility called > the Off-Module Response (OMR) facility, which replaces the Off-Core > Response (OCR) Performance Monitoring of previous processors. > > Legacy microarchitectures used the OCR facility to evaluate off-core > and multi-core off-module transactions. The properly renamed, OMR > facility, improves the OCR capability for scalable coverage of new > memory systems of multi-core module systems. > > Similarly with OCR, 4 additional off-module configuration MSRs > OFFMODULE_RSP_0 ~ OFFMODULE_RSP_3 are introduced to specify > attributes of the off-module transaction. > > For more details about OMR, please refer to section 16.1 "OFF-MODULE > RESPONSE (OMR) FACILITY" in ISE documentation. > > This patch adds support for these 4 OMR events. > > ISE link: https://www.intel.com/content/www/us/en/content-details/869288/intel-architecture-instruction-set-extensions-programming-reference.html > > Signed-off-by: Dapeng Mi > --- > arch/x86/events/intel/core.c | 45 +++++++++++++++++++++++--------- > arch/x86/events/perf_event.h | 5 ++++ > arch/x86/include/asm/msr-index.h | 5 ++++ > 3 files changed, 42 insertions(+), 13 deletions(-) > > diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c > index aad89c9d9514..5970f7c20101 100644 > --- a/arch/x86/events/intel/core.c > +++ b/arch/x86/events/intel/core.c > @@ -3529,17 +3529,24 @@ static int intel_alt_er(struct cpu_hw_events *cpuc, > struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs); > int alt_idx = idx; > > - if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) > - return idx; > - > - if (idx == EXTRA_REG_RSP_0) > - alt_idx = EXTRA_REG_RSP_1; > - > - if (idx == EXTRA_REG_RSP_1) > - alt_idx = EXTRA_REG_RSP_0; > + if (idx == EXTRA_REG_RSP_0 || idx == EXTRA_REG_RSP_1) { > + if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) > + return idx; > + if (++alt_idx > EXTRA_REG_RSP_1) > + alt_idx = EXTRA_REG_RSP_0; > + if (config & ~extra_regs[alt_idx].valid_mask) > + return idx; > + } > > - if (config & ~extra_regs[alt_idx].valid_mask) > - return idx; > + if (idx >= EXTRA_REG_OMR_0 && idx <= EXTRA_REG_OMR_3) { > + if (!(x86_pmu.flags & PMU_FL_HAS_OMR)) > + return idx; > + if (++alt_idx > EXTRA_REG_OMR_3) > + alt_idx = EXTRA_REG_OMR_0; > + if (config & > + ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask) Why minus EXTRA_REG_OMR_0? > + return idx; > + } > > return alt_idx; > } > @@ -3547,16 +3554,28 @@ static int intel_alt_er(struct cpu_hw_events *cpuc, > static void intel_fixup_er(struct perf_event *event, int idx) > { > struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); > - event->hw.extra_reg.idx = idx; > + int omr_idx; > > - if (idx == EXTRA_REG_RSP_0) { > + event->hw.extra_reg.idx = idx; > + switch (idx) { > + case EXTRA_REG_RSP_0: > event->hw.config &= ~INTEL_ARCH_EVENT_MASK; > event->hw.config |= extra_regs[EXTRA_REG_RSP_0].event; > event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0; > - } else if (idx == EXTRA_REG_RSP_1) { > + break; > + case EXTRA_REG_RSP_1: > event->hw.config &= ~INTEL_ARCH_EVENT_MASK; > event->hw.config |= extra_regs[EXTRA_REG_RSP_1].event; > event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; Keep same style? case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1: > + break; > + case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3: > + omr_idx = idx - EXTRA_REG_OMR_0; > + event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK; > + event->hw.config |= 1ULL << (8 + omr_idx); > + event->hw.extra_reg.reg = MSR_OMR_0 + omr_idx; > + break; > + default: > + pr_warn("The extra reg idx %d is not supported.\n", idx); > } > } >