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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEyMDA3MiBTYWx0ZWRfX7hDSiNWDYBLL 205kGwc3EidhV8ntz+SfiI64MbWA+LPfeWkyjC7Rc4t+avd3jnCKthrdfneH1nKiOq1VJJd8GoZ c+eRKAcD50sm5REwfmlwTbAzpI40aYrrH4CB7TLSSHVFfskdKF5qE6A7Hfj+x6evvCOgXKX48vP rMXJrXWvVZlgtlzQjxtVwMtZ5Qhhgf2TyRLxR66Se9RMkrpvApmdeE1HP007jZcsVsUXbl/BJSC z1C9ypxDTEYsggqjjHDPAFIqFczv/qCqyfN2xJspHlUegWfKIF2188K/UnOVWTQFIGR+YlPEO/Z IWmI6ej9E6W0FKIOd/AIYn3OfrtmJXL2g4MvnDnzZB4VHIaDEicOFSE8Kjx1zKf0p3mU78KqU7k TJlRVa9dM1X5pNOB6xEBvS1xekpLHe8mz2+EcD/aCBt9+Z4u1odosxbm88MrA5LJCh4S0uDXTbq AXBV9zeSib/ZNtv5JRw== X-Authority-Analysis: v=2.4 cv=SvAFe/O0 c=1 sm=1 tr=0 ts=6acd2341 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=20alU+YIu2uqf8Hyrg49Cw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=mpA_8Fus6RAmO9hGp9MA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEyMDA3MiBTYWx0ZWRfX90Eo+gtOce2W 51T2/tCYL84Fi88/7mcTXRXh7fWAo4fk56wVGFducZ51F1TO8apxJxhr51LoFf30gpvAjsoLLRF wU8EiAqOPZ+HMlVi/G39DWDNL0eJvlM= X-Proofpoint-ORIG-GUID: cLBV9hRMwCH8_AOgo3s6DiAzBJkOATTY X-Proofpoint-GUID: cLBV9hRMwCH8_AOgo3s6DiAzBJkOATTY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-12_05,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 priorityscore=1501 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610120072 On 10/12/2026 5:39 PM, Dmitry Baryshkov wrote: > On Thu, Oct 08, 2026 at 10:53:48PM +0530, Mahadevan P wrote: >> dpu_crtc_mode_valid() halves the adjusted mode clock whenever the >> hardware has a 3d_mux block, assuming the mode will be driven by two >> layer mixers. Modes no wider than MAX_HDISPLAY_SPLIT are driven by a >> single mixer, so for those the check permits twice the pixel rate the >> datapath can sustain. >> >> Divide by the mixer count the mode will really be driven by, as reported >> by dpu_crtc_num_lm_for_mode(). Split modes still get the halved rate, >> single mixer modes are held to what one mixer sustains, and parts >> without a 3d_mux divide by one. >> >> Assisted-by: LLM >> Signed-off-by: Mahadevan P >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> index 0b51a4c5db57..209b25dbeb6c 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c >> @@ -1631,8 +1631,7 @@ static enum drm_mode_status dpu_crtc_mode_valid(struct drm_crtc *crtc, >> adjusted_mode_clk = dpu_core_perf_adjusted_mode_clk(mode->clock, >> dpu_kms->perf.perf_cfg); >> >> - if (dpu_kms->catalog->caps->has_3d_merge) >> - adjusted_mode_clk /= 2; >> + adjusted_mode_clk /= dpu_crtc_num_lm_for_mode(dpu_kms, mode); > With the 64-bit division fixed, LGTM. When submitting patches to these > drivers please make sure to build for armhf as well as for the arm64. Thanks for reviewing. I’ll replace the division with div_u64() and build-test both armhf and arm64 before sending the next revision. Thanks, Mahadevan > >> >> /* >> * The given mode, adjusted for the perf clock factor, should not exceed >> >> -- >> 2.34.1 >>