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Mon, 19 Nov 2018 01:19:46 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 19 Nov 2018 01:19:44 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 19 Nov 2018 01:19:44 -0600 Received: from [127.0.0.1] (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wAJ7JcJS009623; Mon, 19 Nov 2018 01:19:39 -0600 Subject: Re: [PATCH v2 1/4] dt-bindings: pinctrl: k3: Introduce pinmux definitions To: Nishanth Menon , Vignesh R CC: Rob Herring , Mark Rutland , , , , , Linus Walleij , Tony Lindgren References: <20181113060111.16374-1-vigneshr@ti.com> <20181113060111.16374-2-vigneshr@ti.com> <20181117160502.dhlqbx5qnmdp5iog@kahuna> From: Tero Kristo Message-ID: Date: Mon, 19 Nov 2018 09:19:38 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20181117160502.dhlqbx5qnmdp5iog@kahuna> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/11/2018 18:05, Nishanth Menon wrote: > On 11:31-20181113, Vignesh R wrote: >> The dt-bindings header for TI K3 AM6 SoCs define a set of macros for >> defining pinmux configs in human readable form, instead of raw-coded >> hex values. >> >> Signed-off-by: Vignesh R >> --- >> MAINTAINERS | 1 + >> include/dt-bindings/pinctrl/k3.h | 35 ++++++++++++++++++++++++++++++++ >> 2 files changed, 36 insertions(+) >> create mode 100644 include/dt-bindings/pinctrl/k3.h >> >> diff --git a/MAINTAINERS b/MAINTAINERS >> index fa45ff36fde9..1574ad6d7ead 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -2204,6 +2204,7 @@ S: Supported >> F: Documentation/devicetree/bindings/arm/ti/k3.txt >> F: arch/arm64/boot/dts/ti/Makefile >> F: arch/arm64/boot/dts/ti/k3-* >> +F: include/dt-bindings/pinctrl/k3.h >> >> ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE >> M: Santosh Shilimkar >> diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h >> new file mode 100644 >> index 000000000000..463d845a9b36 >> --- /dev/null >> +++ b/include/dt-bindings/pinctrl/k3.h >> @@ -0,0 +1,35 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * This header provides constants for pinctrl bindings for TI's K3 SoC >> + * family. >> + * >> + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ >> + */ >> +#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H >> +#define _DT_BINDINGS_PINCTRL_TI_K3_H >> + >> +#define PULLUDEN_SHIFT (16) >> +#define PULLTYPESEL_SHIFT (17) >> +#define RXACTIVE_SHIFT (18) >> + >> +#define PULL_DISABLE (1 << PULLUDEN_SHIFT) >> +#define PULL_ENABLE (0 << PULLUDEN_SHIFT) >> + >> +#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) >> +#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) >> + >> +#define INPUT_EN (1 << RXACTIVE_SHIFT) >> +#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) >> + >> +/* Only these macros are expected be used directly in device tree files */ >> +#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) >> +#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) >> +#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) >> +#define PIN_INPUT (INPUT_EN | PULL_DISABLE) >> +#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) >> +#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) > > > Thanks for reducing the combinations down to the minimum needed. We can > worry about the DS and isolation bits when we have a real user for them. > > Acked-by: Nishanth Menon > > Tero: v4.21-rc1 perhaps ? > Yeah, looks fine, queueing up for 4.21. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki